參數(shù)資料
型號(hào)： UPSD3423
廠商： 意法半導(dǎo)體
英文描述： High Speed CMOS Logic Non-Inverting Octal Buffer/Line Drivers with 3-State Outputs 20-SOIC -55 to 125
中文描述： Turbo Plus系列高速渦輪8032 USB和可編程邏輯控制器
文件頁(yè)數(shù)： 167/264頁(yè)
文件大小： 4320K
代理商： UPSD3423
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uPSD34xx - PSD MODULE
PLD #1, Decode PLD (DPLD).
This programma-
ble logic implements memory mapping and is used
to select one of the individual Main Flash memory
segments, one of individual Secondary Flash
memory segments, the SRAM, or the group of
csiop registers when the 8032 presents an ad-
dress to DPLD inputs (see
Figure 75., page 190
).
The DPLD can also optionally drive external chip
select signals on Port D pins. The DPLD also op-
tionally produces two select signals (PSEL0 and
PSEL1) used to enable a special data bus repeat-
er function on Port A, referred to as Peripheral I/O
Mode. There are 69 DPLD input signals which in-
clude: 8032 address and control signals, Page
Register outputs, PSD Module Port pin inputs, and
GPLD logic feedback.
PLD #2, General PLD (GPLD).
This
mable logic is used to create both combinatorial
and sequential general purpose logic (see
Figure
76., page 192
). The GPLD contains 16 Output
Macrocells (OMCs) and 20 Input Macrocells
(IMCs). Output Macrocell registers are unique in
that they have direct connection to the 8032 data
bus allowing them to be loaded and read directly
by the 8032 at runtime through OMC registers in
csiop. This direct access is good for making small
peripheral devices (shifters, counters, state ma-
chines, etc.) that are accessed directly by the 8032
with little overhead. There are 69 GPLD inputs
which include: 8032 address and control signals,
Page Register outputs, PSD Module Port pin in-
puts, and GPLD feedback.
OMCs.
There are two banks of eight OMCs inside
the GPLD, MCELLAB, and MCELLBC, totalling 16
OMCs all together. Each individual OMC is a base
logic element consisting of a flip-flop and some
AND-OR logic (
Figure 77., page 193
). The gener-
al structure of the GPLD with OMCs is similar in
nature to a 22V10 PLD device with the familiar
sum-of-products (AND-OR) construct. True and
compliment versions of 69 input signals are avail-
able to the inputs of a large AND-OR array. AND-
OR array outputs feed into an OR gate within each
OMC, creating up to 10 product-terms for each
OMC. Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flip-
flop within in each OMC to realize sequential logic.
OMC outputs can be used as a buried nodes driv-
ing internal feedback to the AND-OR array, or
OMC outputs can be routed to external pins on
Ports A, B, or C through the OMC Allocator.
program-
OMC Allocator.
The OMC allocator (
Figure
78., page 194
) will route eight of the OMCs from
MCELLAB to pins on either Port A or Port B, and
will route eight of the OMCs from MCELLBC to
pins on either Port B or Port C, based on what is
specified in PSDsoft Express.
IMCs.
Inputs from pins on Ports A, B, and C are
routed to IMCs for conditioning (clocking or latch-
ing) as they enter the chip, which is good for sam-
pling and debouncing inputs. Alternatively, IMCs
can pass port input signals directly to PLD inputs
without
clocking
or
79., page 198
). The 8032 may read the IMCs
asynchronously at any time through IMC registers
in csiop.
Note:
The JTAG signals TDO, TDI, TCK, and TMS
on Port C do not route through IMCs, but go direct-
ly to JTAG logic.
I/O Ports.
For 80-pin uPSD34xx devices, the
PSD Module has 22 individually configurable I/O
pins distributed over four ports (these I/O are in
addition to I/O on MCU Module). For 52-pin
uPSD34xx devices, the PSD Module has 13 indi-
vidually configurable I/O pins distributed over
three ports. See
Figure 85., page 212
for I/O port
pin availability on these two packages.
I/O port pins on the PSD Module (Ports A, B, C,
and D) are completely separate from the port pins
on the MCU Module (Ports 1, 3, and 4). They even
have different electrical characteristics. I/O port
pins on the PSD Module are accessed by csiop
registers, or they are controlled by PLD equations.
Conversely, I/O Port pins on the MCU Module are
controlled by the 8032 SFR registers.
latching
(
Figure
Table 102. General I/O pins on PSD Module
Note: Four pins on Port C are dedicated to JTAG, leaving four pins
for general I/O.
Pkg
Port A
Port B
Port C
Port D
Total
52-pin
0
8
4
1
13
80-pin
8
8
4
2
22
相關(guān)PDF資料
PDF描述
UPSD3423E High Speed CMOS Logic Non-Inverting Octal Buffer/Line Drivers with 3-State Outputs 20-SOIC -55 to 125
UPSD3424 High Speed CMOS Logic Non-Inverting Octal Buffer/Line Drivers with 3-State Outputs 20-SOIC -55 to 125
UPSD3424E High Speed CMOS Logic Non-Inverting Octal Buffer/Line Drivers with 3-State Outputs 20-SOIC -55 to 125
UPSD3433 Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
UPSD3433E Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3433E-40T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433E-40U6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EB40T6 功能描述:8位微控制器 -MCU Turbo 8032 MCU w/USB & Programmable Logic RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EB40U6 功能描述:8位微控制器 -MCU uPSD34x Turbo Plus Fast Turbo 8032 MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3433EV-40T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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