參數(shù)資料
型號(hào): UPSD3254B-40U6T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù): 160/176頁
文件大?。?/td> 1214K
代理商: UPSD3254B-40U6T
μPSD325X DEVICES
160/176
Figure 80. Asynchronous RESET / Preset
Figure 81. Asynchronous Clock Mode Timing (product term clock)
Table 125. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
Rate
Unit
f
MAXA
Maximum Frequency
External Feedback
1/(t
SA
+t
COA
)
38.4
MHz
Maximum Frequency
Internal Feedback (f
CNTA
)
1/(t
SA
+t
COA
–10)
62.5
MHz
Maximum Frequency
Pipelined Data
1/(t
CHA
+t
CLA
)
71.4
MHz
t
SA
Input Setup Time
7
+ 2
+ 10
ns
t
HA
Input Hold Time
8
ns
t
CHA
Clock Input High Time
9
+ 10
ns
t
CLA
Clock Input Low Time
9
+ 10
ns
t
COA
Clock to Output Delay
21
+ 10
– 2
ns
t
ARDA
CPLD Array Delay
Any macrocell
11
+ 2
ns
t
MINA
Minimum Clock Period
1/f
CNTA
16
ns
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCHA
tCLA
tCOA
tHA
tSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859
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