參數(shù)資料
型號(hào)： UPSD3253B
廠商： 意法半導(dǎo)體
英文描述： Two and Three Channel Codewheels
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù)： 136/175頁
文件大?。?/td> 1731K
代理商： UPSD3253B
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
136/175
Automatic Power-down (APD) Unit and Power-
down Mode.
The APD Unit, shown in Figure 69,
puts the PSD MODULE into Power-down Mode by
monitoring the activity of Address Strobe (ALE). If
the APD Unit is enabled, as soon as activity on Ad-
dress Strobe (ALE) stops, a four-bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), Power-down (PDN) goes High, and the
PSD MODULE enters Power-down Mode, as dis-
cussed next.
Power-down Mode.
By default, if you enable the
APD Unit, Power-down Mode is automatically en-
abled. The device enters Power-down Mode if Ad-
dress Strobe (ALE) remains inactive for fifteen
periods of CLKIN (PD1).
The following should be kept in mind when the
PSD MODULE is in Power-down Mode:
I
If Address Strobe (ALE) starts pulsing again, the
PSD MODULE returns to normal Operating
mode. The PSD MODULE also returns to
normal Operating mode if either PSD Chip
Select Input (CSI, PD2) is Low or the RESET
input is High.
I
The MCU address/data bus is blocked from all
memory and PLDs.
I
Various signals can be blocked (prior to Power-
down Mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common CLKIN (PD1).
Note:
Blocking CLKIN (PD1) from the PLDs
does not block CLKIN (PD1) from the APD Unit.
I
All memories enter Standby Mode and are
drawing standby current. However, the PLD and
I/O ports blocks do not
go into Standby Mode
because you don’t want to have to wait for the
logic and I/O to “wake-up” before their outputs
can change. See Table 100 for Power-down
Mode effects on PSD MODULE ports.
I
Typical standby current is of the order of
microamperes. These standby current values
assume that there are no transitions on any PLD
input.
Other Power Saving Options.
The PSD MOD-
ULE offers other reduced power saving options
that are independent of the Power-down Mode.
Except for the SRAM Stand-by and PSD Chip Se-
lect Input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2.
Figure 70. Enable Power-down Flow Chart
Table 100. Power-down Mode’s Effect on Ports
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Peripheral I/O
Tri-State
Enable APD
Set PMMR0 Bit 1 = 1
PSD Module in Power
Down Mode
ALE idle
for 15 CLKIN
clocks
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
AI06609
相關(guān)PDF資料
PDF描述
UPSD3253BV Flash Programmable System Devices with 8032 Microcontroller Core
uPSD3254B-24T1T Flash Programmable System Devices with 8032 Microcontroller Core
uPSD3254B-40T6T Flash Programmable System Devices with 8032 Microcontroller Core
uPSD3254B-40U1T Flash Programmable System Devices with 8032 Microcontroller Core
uPSD3254B-40U6T Flash Programmable System Devices with 8032 Microcontroller Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3253B-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3253B-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3253B-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3253B-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3253B-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*