參數資料
型號: uPSD3234BV-40T1T
廠商: 意法半導體
英文描述: POWERLINE: RP30-S_DEW - 4:1 Wide Input Voltage Range- 30 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- International Safety Standard Approvals- Standard 50.8 x40.6x10.2mm Package- Efficiency to 88%
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器內核
文件頁數: 124/170頁
文件大小: 2717K
代理商: UPSD3234BV-40T1T
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
124/170
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure
65
. The two ports can be
configured to perform one or more of the following
functions:
MCU I/O Mode
CPLD Output – Macrocells McellAB7-
McellAB0 can be connected to Port A or Port
B. McellBC7-McellBC0 can be connected to
Port B or Port C.
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched
address output as per
Table 94., page 121
.
Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
Peripheral Mode – Port A only (80-pin
package)
Figure 65. Port A and Port B Structure
M
DATA OUT
REG.
D
Q
D
G
Q
D
Q
D
Q
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT
A OR B PIN
DATA OUT
ADDRESS
A[7:0]
AI06605
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