參數(shù)資料
型號(hào): uPSD3234AV-40U1T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁(yè)數(shù): 117/170頁(yè)
文件大小: 2717K
代理商: UPSD3234AV-40U1T
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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Product Term Allocator
The CPLD has a Product Term Allocator. PSDsoft
uses the Product Term Allocator to borrow and
place product terms from one macrocell to anoth-
er. The following list summarizes how product
terms are allocated:
McellAB0-McellAB7 all have three native
product terms and may borrow up to six more
McellBC0-McellBC3 all have four native
product terms and may borrow up to five more
McellBC4-McellBC7 all have four native
product terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.
This is called product term expansion. PSDsoft
Express performs this expansion as needed.
Loading and Reading the Output Macrocells
(OMC).
The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP block (see the
section
entitled
I/O
MODULE), page 119
). The flip-flops in each of the
16 Output Macrocells (OMC) can be loaded from
the data bus by a MCU. Loading the Output Mac-
rocells (OMC) with data from the MCU takes prior-
ity over internal functions. As such, the preset,
clear, and clock inputs to the flip-flop can be over-
ridden by the MCU. The ability to load the flip-flops
and read them back is useful in such applications
as loadable counters and shift registers, mailbox-
es, and handshaking protocols.
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of WRITE Strobe (WR,
edge loading) or during the time that WRITE
Strobe (WR) is active (level loading). The method
of loading is specified in PSDsoft Express Config-
uration.
PORTS
(PSD
Figure 61. CPLD Output Macrocell
PT
ALLOCATOR
MASK
REG.
PT CLK
PT
PT
PT
CLKIN
FEEDBACK (.FB)
PORT INPUT
A
P
MUX
MUX
POLARITY
SELECT
LD
IN
CLR
Q
PR
DIN
COMB/REG
SELECT
PORT
DRIVER
INPUT
MACROCELL
I/O PIN
MACROCELL
ALLOCATOR
MCU DATA BUS
D[7:0]
DIRECTION
REGISTER
CLEAR (.RE)
PROGRAMMABLE
WR
ENABLE (.OE)
PRESET(.PR)
RD
MACROCELL CS
AI06617
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