參數(shù)資料
型號: uPSD3234AV-24T6T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù): 169/170頁
文件大?。?/td> 2717K
代理商: UPSD3234AV-24T6T
169/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
REVISION HISTORY
Table 150. Document Revision History
Table 151. Device Functional Change History
Note: Date Code is the 6th to the 9th digit of the Trace Code on top of the device.
Date
Version
Revision Details
November 2002
1.0
First Issue
27-Feb-03
1.1
Updates: product information (Figure
3
,
4
, Table
1
,
2
); port information (Figure
17
,
18
,
Table
30
); interface information (Figure
30
, Table
44
); remove programming guide; PSD
Module information (Figure
50
,
51
, Table
85
); PLD information (Figure
58
,
59
, Table
91
,
92
,
93
); electrical characteristics (Table
118
,
119
,
135
,
136
)
02-Sep-03
1.2
Updated references for Product Catalog
04-Feb-04
2.0
Reformatted; corrected mechanical dimensions (Table
148
)
05-Jul-04
3.0
Reformatted; added EMC characteristics (Table
109
,
110
,
111
)
04-Nov-04
4.0
Updates according to data brief change request (Figure
3
,
4
; Table
1
,
2
,
116
)
Functional Change
After Date Code 0242
Date Code 0242 and before
PWM Block
An 8-bit, Programmable PWM 4 channel
and the associated registers are added.
Only PWM0-PWM3 channels are
available.
DDC SRAM Mapping
When DDC is disabled, the data space
FF00h-FFFFh assigned to DDC SRAM is
available for external data mapping. The
SWENB Bit definition in the DDCON
Register is modified.
Data space FF00h-FFFFh is dedicated to
DDC SRAM.
USB Reset Function
1.
Option to block USB generated reset
from resetting the MCU/PSD modules.
Allow USB Reset Flag (RSTF) to
interrupt MCU.
Add RSTE and RSTFIE Bits to the
UIEN Interrupt Enable Register.
2.
3.
USB-generated reset always resets both,
the USB and the MCU/PSD modules.
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