- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361591 > uPSD3234AV-24T6T (意法半導(dǎo)體) Flash Programmable System Devices with 8032 Microcontroller Core PDF資料下載
參數(shù)資料
| 型號(hào)： | uPSD3234AV-24T6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核 |
| 文件頁(yè)數(shù)： | 134/170頁(yè) |
| 文件大?。?/td> | 2717K |
| 代理商： | UPSD3234AV-24T6T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)當(dāng)前第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
134/170
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface pins (TMS, TCK, TDI,
TDO) are dedicated pins on Port C (see Table
106
). All memory blocks (primary and secondary
Flash memory), PLD logic, and PSD Module Con-
figuration Register Bits may be programmed
through the JTAG Serial Interface block. A blank
device can be mounted on a printed circuit board
and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank device (as shipped from the
factory or after erasure), four pins on Port C are
the basic JTAG signals TMS, TCK, TDI, and TDO.
Standard JTAG Signals
At power-up, the standard JTAG pins are inputs,
waiting for a JTAG serial command from an exter-
nal JTAG controller device (such as FlashLINK or
Automated Test Equipment). When the enabling
command is received, TDO becomes an output
and the JTAG channel is fully functional. The
same command that enables the JTAG channel
may optionally enable the two additional JTAG sig-
nals, TSTAT and TERR.
The RESET input to the uPS3200 should be active
during JTAG programming. The active RESET
puts the MCU module into RESET Mode while the
PSD Module is being programmed. See Applica-
tion Note AN1153 for more details on JTAG In-
System Programming (ISP).
The uPSD323X Devices supports JTAG In-Sys-
tem-Configuration (ISC) commands, but not
Boundary Scan. The PSDsoft Express software
tool and FlashLINK JTAG programming cable im-
plement the JTAG In-System-Configuration (ISC)
commands.
Table 106. JTAG Port Signals
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENABLE” command received
over the four standard JTAG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on uPDS
signals instead of having to scan the status out se-
rially using the standard JTAG channel. See Appli-
cation Note AN1153
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set (RESET) pulse is received after an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy de-
scribed in
Ready/Busy (PC3), page 99
. TSTAT is
High when the PSD Module device is in READ
Mode (primary and secondary Flash memory con-
tents can be read). TSTAT is Low when Flash
memory Program or Erase cycles are in progress,
and also when data is being written to the second-
ary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand.
Security and Flash memory Protection
When the Security Bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
INITIAL DELIVERY STATE
When delivered from ST, the uPSD323X Devices
have all bits in the memory and PLDs set to '1.'
The code, configuration, and PLD logic are loaded
using the programming procedure. Information for
programming the device is available directly from
ST. Please contact your local sales representa-
tive.
Port C Pin
JTAG Signals
Description
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status (optional)
PC4
TERR
Error Flag (optional)
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| uPSD3234AV-40T1T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3234AV-40T6T | Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233BV | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3233BV-40T6T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3233BV-40U1T | Flash Programmable System Devices with 8032 Microcontroller Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3234AV-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3234AV-24U1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3234AV-24U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3234AV-24U6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3234AV-40T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。