參數(shù)資料
型號: UPSD3234A
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器內(nèi)核
文件頁數(shù): 37/170頁
文件大?。?/td> 2717K
代理商: UPSD3234A
37/170
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Interrupt Priority Structure
Each interrupt source can be assigned one of two
priority levels. Interrupt priority levels are defined
by the interrupt priority special function register IP
and IPA.
0 = low priority
1 = high priority
A low priority interrupt may be interrupted by a
high priority interrupt level interrupt. A high priority
interrupt routine cannot be interrupted by any oth-
er interrupt source. If two interrupts of different pri-
ority occur simultaneously, the high priority level
request is serviced. If requests of the same priority
are received simultaneously, an internal polling
sequence determines which request is serviced.
Thus, within each priority level, there is a second
priority structure determined by the polling se-
quence.
Interrupts Enable Structure
Each interrupt source can be individually enabled
or disabled by setting or clearing a bit in the inter-
rupt enable special function register IE and IEA. All
interrupt source can also be globally disabled by
clearing Bit EA in IE.
Table 19. Priority Levels
Table 20. Description of the IE Bits
Table 21. Description of the IEA Bits
Source
Priority with Level
Int0
0 (highest)
2nd USART
1
Timer 0
2
I2C
3
Int1
4
DDC
5
Timer 1
6
USB
7
1st USART
8
Timer 2+EXF2
9 (lowest)
Bit
Symbol
Function
7
EA
Disable all interrupts:
0: no interrupt with be acknowledged
1: each interrupt source is individually enabled or disabled by setting or clearing its
enable bit
6
Reserved
5
ET2
Enable Timer 2 Interrupt
4
ES
Enable USART Interrupt
3
ET1
Enable Timer 1 Interrupt
2
EX1
Enable external Interrupt (Int1)
1
ET0
Enable Timer 0 Interrupt
0
EX0
Enable external Interrupt (Int0)
Bit
Symbol
Function
7
EDDC
Enable DDC Interrupt
6
Not used
5
Not used
4
ES2
Enable 2nd USART Interrupt
3
Not used
2
Not used
1
EI2C
Enable I2C Interrupt
0
EUSB
Enable USB Interrupt
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