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    參數(shù)資料
    型號: UPSD3234A
    廠商: 意法半導體
    英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
    中文描述: 閃存可編程系統(tǒng)設備與8032微控制器內(nèi)核
    文件頁數(shù): 126/170頁
    文件大?。?/td> 2717K
    代理商: UPSD3234A
    uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
    126/170
    Port D – Functionality and Structure
    Port D has two I/O pins (only one pin, PD1, in the
    52-pin package). See Figure
    67
    and
    Figure
    68., page 127
    . This port does not support Address
    Out Mode, and therefore no Control Register is re-
    quired. Of the eight bits in the Port D registers,
    only Bits 2 and 1 are used to configure pins PD2
    and PD1.
    Port D can be configured to perform one or more
    of the following functions:
    MCU I/O Mode
    CPLD Output – External Chip Select (ECS1-
    ECS2)
    CPLD Input – direct input to the CPLD, no
    Input Macrocells (IMC)
    Slew rate – pins can be set up for fast slew
    rate
    Port D pins can be configured in PSDsoft Express
    as input pins for other dedicated functions:
    CLKIN (PD1) as input to the macrocells flip-
    flops and APD counter
    PSD Chip Select Input (CSI, PD2). Driving this
    signal High disables the Flash memory, SRAM
    and CSIOP.
    Figure 67. Port D Structure
    M
    DATA OUT
    REG.
    D
    Q
    D
    Q
    WR
    WR
    ECS[2:1]
    READ MUX
    P
    D
    B
    CPLD-INPUT
    DIR REG.
    DATA IN
    ENABLE PRODUCT
    TERM (.OE)
    OUTPUT
    SELECT
    OUTPUT
    MUX
    PORT D PIN
    DATA OUT
    AI06606
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