參數(shù)資料
型號: UPSD3233BV
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù): 160/170頁
文件大?。?/td> 2717K
代理商: UPSD3233BV
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
160/170
Figure 85. Reset (RESET) Timing
Table 140. Reset (RESET) Timing (5V Devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 141. Reset (RESET) Timing (3V Devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 142. V
STBYON
Definitions Timing (5V Devices)
Symbol
Note: 1. V
STBYON
timing is measured at V
CC
ramp rate of 2ms.
Table 143. V
STBYON
Timing (3V Devices)
Symbol
Note: 1. V
STBYON
timing is measured at V
CC
ramp rate of 2ms.
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
(1)
150
ns
t
NLNH–PO
Power-on Reset Active Low Time
1
ms
t
NLNH–A
Warm RESET
(2)
25
μ
s
t
OPR
RESET High to Operational Device
120
ns
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
(1)
300
ns
t
NLNH–PO
Power-on Reset Active Low Time
1
ms
t
NLNH–A
Warm RESET
(2)
25
μ
s
t
OPR
RESET High to Operational Device
300
ns
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1)
20
μs
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1)
20
μs
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
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