參數(shù)資料
型號: UPSD3214AV-24U1T
廠商: 意法半導體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設備與8032微控制器核心和64Kbit SRAM的
文件頁數(shù): 62/176頁
文件大?。?/td> 1081K
代理商: UPSD3214AV-24U1T
μ
PSD323X
62/176
Baud Rates.
The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = fosc / 12
The baud rate in Mode 2 depends on the value of
Bit SMOD = 0 (which is the value on reset), the
baud rate is 1/64 the oscillatorfrequency. If SMOD
= 1, the baud rate is 1/32 the oscillator frequency.
Mode 2 Baud Rate = (2
SMOD
/ 64) x fosc
In the
μ
PSD323X Devices, the baud rates in
Modes 1 and 3 are determined by the Timer 1
overflow rate.
Using Timer 1 to Generate Baud Rates.
When
Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by
the Timer 1 overflow rate and the value of SMOD
as follows (see:
Mode 1,3 Baud Rate = (2
SMOD
/ 32) x (Timer 1
overflow Rate)
The Timer 1 interruptshould be disabled inthis ap-
plication. TheTimer itself can be configured for ei-
ther “timer” or “counter”operation, and in any of its
3 running modes. In the most typical applications,
it is configured for “timer” operation, inthe Auto-re-
load Mode (high nibble of TMOD = 0010B). In that
case the baud rate is given by the formula:
Mode 1,3 Baud Rate = = (2
SMOD
/ 32) x (fosc / 12
x [256 - (TH1)]
One can achieve very low baud rates with Timer 1
by leaving the Timer 1 interrupt enabled, and con-
figuring the Timer to run as a 16-bit timer (high nib-
ble of TMOD = 0001B), and using the Timer 1
interrupt to do a 16-bit software reload. Figure 22
lists various commonly used baud rates and how
they can be obtained from Timer 1.
Using Timer/Counter 2 to Generate Baud
Rates.
In the
μ
PSD323X Devices,Timer 2 select-
ed as the baud rate generator by setting TCLK
and/or RCLK (see Figure 22, page 55 Timer/
Counter 2 Control Register (T2CON)).
Note:
The baud rate for transmit and receive can
be simultaneously different. Setting RCLK and/or
TCLK puts Timer into its Baud Rate Generator
Mode.
The RCLK and TCLK Bits in the T2CON register
configure UART 1. The RCLK1 and TCLK1 Bits in
the PCON register configure UART 2.
The Baud Rate Generator Mode is similar to the
Auto-reload Mode, in thata rollover in TH2causes
the Timer 2 registersto be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which
are preset by software.
Now, the baud rates in Modes 1 and 3 are deter-
mined at Timer 2’s overflow rate as follows:
Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16
Table 45. Timer 1-Generated Commonly Used Baud Rates
Baud Rate
f
OSC
SMOD
Timer 1
C/T
Mode
Reload Value
Mode 0 Max: 1MHz
12MHz
X
X
X
X
Mode 2 Max: 375K
12MHz
1
X
X
X
Modes 1, 3: 62.5K
12MHz
1
0
2
FFh
19.2K
11.059MHz
1
0
2
FDh
9.6K
11.059MHz
0
0
2
FDh
4.8K
11.059MHz
0
0
2
FAh
2.4K
11.059MHz
0
0
2
F4h
1.2K
11.059MHz
0
0
2
E8h
137.5
11.059MHz
0
0
2
1Dh
110
6MHz
0
0
2
72h
110
12MHz
0
0
1
FEEBh
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