參數(shù)資料
型號: UPSD3214AV-24U1T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和64Kbit SRAM的
文件頁數(shù): 122/176頁
文件大小: 1081K
代理商: UPSD3214AV-24U1T
μ
PSD323X
122/176
Decode PLD (DPLD)
The DPLD, shown in Figure 59,is used for decod-
ing the address for PSD MODULE and external
components. The DPLD can be used to generate
the following decode signals:
I
8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
I
4 Sector Select (CSBOOT0-CSBOOT3)signals
for the secondary Flash memory (three product
terms each)
I
1 internal SRAM Select (RS0) signal (two
product terms)
I
1 internalCSIOP Select signal(selectsthe PSD
MODULE registers)
I
2 internal Peripheral Select signals (Peripheral
I/O Mode).
Figure 59. DPLD Logic Array
Note: 1. Port A inputs are not available in the 52-pin package
2. Inputs from the MCU module
(INPUTS)
(24)
(8)
(16)
(1)
PDN (APD OUTPUT)
I/O PORTS (PORT A,B,C)1
MCELLBC.FB [7:0] (FEEDBACKS)
(8)
PGR0-PGR7
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
A[15:0]2
(2)
(4)
PD[2:1]
PSEN, RD, WR, ALE2
(1)
(1)
RESET2
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 PRIMARY
FLASH
MEMORY SECTOR
SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL
I/O
MODE SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
2
AI06601
FS1
FS2
FS3
FS6
FS5
FS4
1
1
1
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