參數(shù)資料
型號: UPSD3212CV-24T6
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032具有USB和可編程邏輯控制器
文件頁數(shù): 125/163頁
文件大小: 2844K
代理商: UPSD3212CV-24T6
125/163
uPSD3212A, uPSD3212C, uPSD3212CV
Table 100. Power Management Mode Registers PMMR2
Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.
Table 101. APD Counter Operation
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
PLD Array
WR
0 = on WR input to the PLD AND Array is connected.
1 = off WR input to PLD AND Array is disconnected, saving power.
Bit 3
PLD Array
RD
0 = on RD input to the PLD AND Array is connected.
1 = off RD input to PLD AND Array is disconnected, saving power.
Bit 4
PLD Array
PSEN
0 = on PSEN input to the PLD AND Array is connected.
1 = off PSEN input to PLD AND Array is disconnected, saving power.
Bit 5
PLD Array
ALE
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
APD Enable Bit
ALE Level
APD Counter
0
X
Not Counting
1
Pulsing
Not Counting
1
0 or 1
Counting (Generates PDN after 15 Clocks)
相關(guān)PDF資料
PDF描述
UPSD3212CV-24U6 Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
uPSD3212C Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3212CV Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3212 Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器件)
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參數(shù)描述
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