參數(shù)資料
型號： UPSD3212CV-24T6
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032具有USB和可編程邏輯控制器
文件頁數(shù)： 113/163頁
文件大?。?/td> 2844K
代理商： UPSD3212CV-24T6
113/163
uPSD3212A, uPSD3212C, uPSD3212CV
I/O PORTS (PSD MODULE)
There are four programmable I/O ports: Ports A, B,
C, and D in the PSD MODULE. Each of the ports
is eight bits except Port D, which is 3 bits. Each
port pin is individually user configurable, thus al-
lowing multiple functions per port. The ports are
configured using PSDsoft Express Configuration
or by the MCU writing to on-chip registers in the
CSIOP space. Port A is not available in the 52-pin
package.
The topics discussed in this section are:
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
59
. Individual Port architectures
are shown in
Figure 61., page 118
to
Figure
64., page 121
. In general, once the purpose for a
■
■
■
■
■
port pin has been defined, that pin is no longer
available for other purposes. Exceptions are not-
ed.
As shown in Figure
59
, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS1-ECS2) from the
CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
■
■
■
■
Figure 59. General I/O Port Architecture
M
DATA OUT
REG.
D
Q
D
G
Q
D
Q
D
Q
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
EXT CS
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
AI06604
相關(guān)PDF資料
PDF描述
UPSD3212CV-24U6 Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
uPSD3212C Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3212CV Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3212 Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器件)
UPSD3215A-24T1 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3212CV-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212CV-24U1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM
UPSD3212CV-24U6 功能描述:8位微控制器 -MCU 3.0V 512K 24MHz RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
UPSD3212CV-24U6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 MCU with USB and Programmable Logic
UPSD3212CV-40T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM
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