參數(shù)資料
型號(hào)： UPD78P368AKL-S
廠商： NEC Corp.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:66; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:18-35 RoHS Compliant: No
中文描述： 16 / 8位單片機(jī)
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 545K
代理商： UPD78P368AKL-S
26
m
PD78P368A
AC CHARACTERISTICS (T
A
= –40 to +85 °C, V
DD
= +5 V ±10 %, V
SS
= 0 V, C
L
= 100 pF, f
XX
= 8 MHz)
Read/Write Operation (when general-purpose memory is connected)
Parameter
Symbol
Conditions
Min.
Max.
Unit
System clock cycle time
t
CYK
62.5
166.7
ns
Address setup time (vs. ASTB
)
t
SAST
7
ns
Address hold time (vs. ASTB
)
t
HSTA
11
ns
RD
address float time
t
FRA
24
ns
Address
data input time
t
DAID
100
ns
RD
data input time
t
DRID
49
ns
ASTB
RD
delay time
t
DSTR
15
ns
Data hold time (vs. RD
)
t
HRID
0
ns
RD
address active time
t
DRA
17
ns
RD low-level width
t
WRL
63
ns
ASTB high-level width
t
WSTH
14
ns
WR
data output time
t
DWOD
21
ns
ASTB
WR
delay time
t
DSTW
15
ns
WR
ASTB
delay time
t
DWST
78
ns
Data setup time (vs. WR
)
t
SODW
57
ns
Data hold time (vs. WR
)
t
HWOD
8
ns
WR low-level width
t
WWL
63
ns
t
CYK
-dependent Bus Timing Definition
Parameter
Arithmetic expression
Min./Max.
Unit
t
SAST
(0.5 + a) T – 24
Min.
ns
t
HSTA
0.5T – 20
Min.
ns
t
WSTH
(0.5 + a) T – 17
Min.
ns
t
DSTR
0.5T – 16
Min.
ns
t
WRL
(1.5 + n) T – 30
Min.
ns
t
DAID
(2.5 + a + n) T – 56
Max.
ns
t
DRID
(1.5 + n) T – 44
Max.
ns
t
DRA
0.5T – 14
Min.
ns
t
DSTW
0.5T – 16
Min.
ns
t
DWST
1.5T – 15
Min.
ns
t
WWL
(1.5 + n) T – 30
Min.
ns
t
DWOD
0.5T – 10
Max.
ns
t
SODW
(1 + n) T – 5
Min.
ns
Remarks 1.
T = t
CYK
= 1/f
CLK
(f
CLK
refers to the internal system clock frequency.)
2.
a becomes 1 when the address wait is inserted. Otherwise, it becomes 0.
3.
n refers to the number of wait cycles that is inserted by specifying the PWC register.
4.
Only the bus timings indicated in this table depend on t
CYK
.
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