![](http://datasheet.mmic.net.cn/Renesas-Electronics-America/UPD78F9418AGC-8BT-A_datasheet_99866/UPD78F9418AGC-8BT-A_18.png)
16
User’s Manual U13952EJ3V1UD
LIST OF FIGURES (1/5)
Figure No.
Title
Page
2-1
Pin I/O Circuits .............................................................................................................................................42
3-1
Memory Map (
PD789405A and PD789415A)...........................................................................................44
3-2
Memory Map (
PD789406A and PD789416A)...........................................................................................45
3-3
Memory Map (
PD789407A and PD789417A)...........................................................................................46
3-4
Memory Map (
PD78F9418A)......................................................................................................................47
3-5
Data Memory Addressing (
PD789405A and PD789415A) .......................................................................50
3-6
Data Memory Addressing (
PD789406A and PD789416A) .......................................................................51
3-7
Data Memory Addressing (
PD789407A and PD789417A) .......................................................................52
3-8
Data Memory Addressing (
PD78F9418A) ..................................................................................................53
3-9
Program Counter Configuration....................................................................................................................54
3-10
Program Status Word Configuration.............................................................................................................54
3-11
Stack Pointer Configuration..........................................................................................................................56
3-12
Data Saved to Stack Memory.......................................................................................................................56
3-13
Data Restored from Stack Memory ..............................................................................................................56
3-14
General-Purpose Register Configuration......................................................................................................57
4-1
Port Types ....................................................................................................................................................70
4-2
Block Diagram of P00 to P03 .......................................................................................................................72
4-3
Block Diagram of P20...................................................................................................................................73
4-4
Block Diagram of P21...................................................................................................................................74
4-5
Block Diagram of P22 and P24 ....................................................................................................................75
4-6
Block Diagram of P23...................................................................................................................................76
4-7
Block Diagram of P25 to P27 .......................................................................................................................77
4-8
Block Diagram of P40 to P45 .......................................................................................................................78
4-9
Block Diagram of P46 and P47 ....................................................................................................................79
4-10
Block Diagram of P50 to P53 .......................................................................................................................80
4-11
Block Diagram of P60 and P61 ....................................................................................................................81
4-12
Block Diagram of P62 to P66 .......................................................................................................................82
4-13
Block Diagram of P80 to P87 .......................................................................................................................83
4-14
Block Diagram of P90 to P93 .......................................................................................................................84
4-15
Format of Port Mode Register ......................................................................................................................86
4-16
Format of Pull-Up Resistor Option Register 0 ..............................................................................................86
4-17
Format of Pull-Up Resistor Option Register 1 ..............................................................................................87
4-18
Format of Pull-Up Resistor Option Register 2 ..............................................................................................87
5-1
Block Diagram of Clock Generator ...............................................................................................................90
5-2
Format of Processor Clock Control Register ................................................................................................91
5-3
Format of Suboscillation Mode Register.......................................................................................................92
5-4
Format of Subclock Control Register............................................................................................................93
5-5
External Circuit of Main System Clock Oscillator..........................................................................................94
5-6
External Circuit of Subsystem Clock Oscillator.............................................................................................95
5-7
Examples of Incorrect Resonator Connection ..............................................................................................96
5-8
Switching Between System Clock and CPU Clock .....................................................................................100