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CHAPTER 5 CLOCK GENERATOR
User’s Manual U19678EJ1V1UD
265
Table 5-10. Maximum Number of Clocks Required for fMAIN
fSUB
Set Value Before Switchover
Set Value After Switchover
CSS
0
(fCLK = fMAIN)
1
(fCLK = fSUB)
fMAIN<fSUB
2 + fMAIN/fSUB clock
0
(fCLK = fMAIN)
fMAIN>fSUB
1 + 2fMAIN/fSUB clock
fMAIN<fSUB
1 + 2fSUB/fMAIN clock
1
(fCLK = fSUB)
fMAIN>fSUB
2 + fSUB/fMAIN clock
Remarks 1. The number of clocks listed in Table 5-8 to Table 5-10 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Table 5-8 to Table 5-10 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fIH = 8 MHz, fMX = 10 MHz)
1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8
→ 2 clocks
5.6.8 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-11. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
Internal high-speed
oscillation clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock.)
HIOSTOP = 1
X1 clock
External main system clock
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock.)
MSTOP = 1
Subsystem clock
Note
CLS = 0
(The CPU is operating on a clock other than the subsystem clock.)
XTSTOP = 1
40 MHz internal high-speed
oscillation clock
SELDSC = 0, DSPO = 0
(The main system clock is operating on a clock other than the 40 MHz
internal high-speed oscillation clock.)
DSCON = 0
Note
The 78K0R/IB3 doesn’t have the subsystem clock.