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70
μ
PD784224, 784225, 784224Y, 784225Y
Data Sheet U12376EJ1V0DS00
AC Characteristics (T
A
=
40
°
C to +85
°
C, V
DD
= V
DD0
= V
DD1
= AV
DD
= 1.8 to 5.5 V, V
SS
= V
SS0
= V
SS1
= AV
SS
= 0 V)
(2) External wait timing (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input time from address to
WAIT
↓
t
DAWT
V
DD
= 5.0 V
±
10%
(2 + a) T
40
ns
V
DD
= 3.0 V
±
10%
(2 + a) T
60
ns
V
DD
= 2.0 V
±
10%
(2 + a) T
300
ns
Input time from ASTB
↓
to
WAIT
↓
t
DSTWT
V
DD
= 5.0 V
±
10%
1.5T
40
ns
V
DD
= 3.0 V
±
10%
1.5T
60
ns
V
DD
= 2.0 V
±
10%
1.5T
260
ns
Hold time from ASTB
↓
to
WAIT
t
HSTWT
V
DD
= 5.0 V
±
10%
(0.5 + n) T + 5
ns
V
DD
= 3.0 V
±
10%
(0.5 + n) T + 10
ns
V
DD
= 2.0 V
±
10%
(0.5 + n) T + 30
ns
Delay time from ASTB
↓
to
WAIT
↑
t
DSTWTH
V
DD
= 5.0 V
±
10%
(1.5 + n) T
40
ns
V
DD
= 3.0 V
±
10%
(1.5 + n) T
60
ns
V
DD
= 2.0 V
±
10%
(1.5 + n) T
90
ns
Input time from RD
↓
to
WAIT
↓
t
DRWTL
V
DD
= 5.0 V
±
10%
T
40
ns
V
DD
= 3.0 V
±
10%
T
60
ns
V
DD
= 2.0 V
±
10%
T
70
ns
Hold time from RD
↓
to
WAIT
↓
t
HRWT
V
DD
= 5.0 V
±
10%
nT + 5
ns
V
DD
= 3.0 V
±
10%
nT + 10
ns
V
DD
= 2.0 V
±
10%
nT + 30
ns
Delay time from RD
↓
to
WAIT
↑
t
DRWTH
V
DD
= 5.0 V
±
10%
(1 + n) T
40
ns
V
DD
= 3.0 V
±
10%
(1 + n) T
60
ns
V
DD
= 2.0 V
±
10%
(1 + n) T
90
ns
Input time from WAIT
↑
to
data
t
DWTID
V
DD
= 5.0 V
±
10%
0.5T
5
ns
V
DD
= 3.0 V
±
10%
0.5T
10
ns
V
DD
= 2.0 V
±
10%
0.5T
30
ns
Delay time from WAIT
↑
to
RD
↑
t
DWTR
V
DD
= 5.0 V
±
10%
0.5T
ns
V
DD
= 3.0 V
±
10%
0.5T
ns
V
DD
= 2.0 V
±
10%
0.5T + 5
ns
Delay time from WAIT
↑
to
WR
↑
t
DWTW
V
DD
= 5.0 V
±
10%
0.5T
ns
V
DD
= 3.0 V
±
10%
0.5T
ns
V
DD
= 2.0 V
±
10%
0.5T + 5
ns
Delay time from WR
↓
to
WAIT
↓
t
DWWTL
V
DD
= 5.0 V
±
10%
T
40
ns
V
DD
= 3.0 V
±
10%
T
60
ns
V
DD
= 2.0 V
±
10%
T
90
ns
Remark
T: t
CYK
= 1/f
XX
(f
XX
: Main system clock frequency)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)