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參數(shù)資料
| 型號： | UPD784037YGK |
| 廠商： | NEC Corp. |
| 英文描述： | TRANS PREBIASED DUAL NPN SOT363 |
| 中文描述： | 16-/8-bit的單晶片微控制器 |
| 文件頁數(shù)： | 32/94頁 |
| 文件大?。?/td> | 503K |
| 代理商： | UPD784037YGK |
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μ
PD784035Y, 784036Y, 784037Y, 784038Y
32
Table 7-1. Port Functions
Port Name
Pin Name
Function
Specification of Pull-up Resistor
Connection by Software
Port 0
P00 to P07
Can be set in input or output mode in
All port pins in input mode
1-bit units.
Can operate as 4-bit real-time output port
(P00 through P03 and P04 through P07)
Can drive transistor.
Port 1
P10 to P17
Can be set in input or output mode in
All port pins in input mode
1-bit units.
Can drive LEDs.
Port 2
P20 to P27
Input port
In 6-bit units (P22 through P27)
Port 3
P30 to P37
Can be set in input or output mode in
All port pins in input mode
1-bit units.
Port 4
P40 to P47
Can be set in input or output mode in
All port pins in input mode
1-bit units.
Can drive LEDs.
Port 5
P50 to P57
Can be set in input or output mode in
All port pins in input mode
1-bit units.
Can drive LEDs.
Port 6
P60 to P67
Can be set in input or output mode in
All port pins in input mode
1-bit units.
Port 7
P70 to P77
Can be set in input or output mode in
–
1-bit units.
7.2 Clock Generation Circuit
An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider
circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit
to reduce the current consumption.
Figure 7-2. Block Diagram of Clock Generation Circuit
Remark
f
XX
: oscillation frequency or external clock input
f
CLK
: internal operating frequency
X1
X2
f
XX
1/2
1/2
1/2
1/2
UART/IOE
INTP0 noise reduction circuit
Oscillation stabilization timer
f
XX
/2
f
CLK
CPU
Peripheral circuit
Oscillation
circuit
S
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