參數(shù)資料
型號(hào)： UPD784037
廠商： NEC Corp.
英文描述： 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16-/8-bit的單晶片微控制器
文件頁(yè)數(shù)： 69/94頁(yè)
文件大?。?/td> 503K
代理商： UPD784037
69
μ
PD784035Y, 784036Y, 784037Y, 784038Y
(1) Read/write operation (2/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Data setup time (to WR
↑
)
t
SODW
V
DD
= +5.0 V
±
10%
(1.5+n)T–30
ns
(1.5+n)T–40
ns
Data hold time
t
HWOD
V
DD
= +5.0 V
±
10%
0.5T–5
ns
(from WR
↑
)
Note
ASTB
↑
delay time
(from WR
↑
)
0.5T–25
ns
t
DWST
0.5T–12
ns
WR low-level width
t
WWL
V
DD
= +5.0 V
±
10%
(1.5+n)T–30
ns
(1.5+n)T–40
ns
Note
The hold time includes the time during which V
OH1
and V
OL1
are held under the load conditions of C
L
=
50 pF and R
L
= 4.7 k
.
Remark
T: T
CYK
(system clock cycle time)
n: Number of wait states (n
≥
0)
(2) Bus hold timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Float delay time from
HLDRQ
↑
HLDAK
↑
delay time
from HLDRQ
↑
t
FHQC
(6+a+n)T+50
ns
t
DHQHHAH
V
DD
= +5.0 V
±
10%
(7+a+n)T+30
ns
(7+a+n)T+40
ns
HLDAK
↑
delay time
from float
t
DCFHA
1T+30
ns
HLDAK
↓
delay time
from HLDRQ
↓
t
DHQLHAL
V
DD
= +5.0 V
±
10%
2T+40
ns
2T+60
ns
Active delay time from
HLDAK
↓
t
DHAC
V
DD
= +5.0 V
±
10%
1T–20
ns
1T–30
ns
Remark
T: T
CYK
(system clock cycle time)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n
≥
0)
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