參數(shù)資料
型號： UPD784037
廠商： NEC Corp.
英文描述： 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16-/8-bit的單晶片微控制器
文件頁數(shù)： 68/94頁
文件大?。?/td> 503K
代理商： UPD784037
μ
PD784035Y, 784036Y, 784037Y, 784038Y
68
AC CHARACTERISTICS (T
A
= –40 to +85
°
C, V
DD
= AV
DD
= +2.7 to 5.5 V, V
SS
= AV
SS
= 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time
t
SAST
V
DD
= +5.0 V
±
10%
(0.5+a)T–15
ns
(0.5+a)T–31
ns
ASTB high-level width
t
WSTH
V
DD
= +5.0 V
±
10%
(0.5+a)T–17
ns
(0.5+a)T–40
ns
Address hold time
(from ASTB
↓
)
t
HSTLA
V
DD
= +5.0 V
±
10%
0.5T–24
ns
0.5T–34
ns
Address hold time
(from RD
↑
)
t
HRA
0.5T–14
ns
RD
↓
delay time from
address
t
DAR
V
DD
= +5.0 V
±
10%
(1+a)T–9
ns
(1+a)T–15
ns
Address float time
(from RD
↓
)
t
FRA
0
ns
Data input time from
address
t
DAID
V
DD
= +5.0 V
±
10%
(2.5+a+n)T–37
ns
(2.5+a+n)T–52
ns
Data input time from
ASTB
↓
t
DSTID
V
DD
= +5.0 V
±
10%
(2+n)T–40
ns
(2+n)T–60
ns
Data input time from
RD
↓
t
DRID
V
DD
= +5.0 V
±
10%
(1.5+n)T–50
ns
(1.5+n)T–70
ns
RD
↓
delay time from
ASTB
↓
Data hold time
(from RD
↑
)
t
DSTR
0.5T–9
ns
t
HRID
0
ns
Address active time
from RD
↑
t
DRA
After program is read
V
DD
= +5.0 V
±
10%
0.5T–8
ns
0.5T–12
ns
After data is read
V
DD
= +5.0 V
±
10%
1.5T–8
ns
1.5T–12
ns
ASTB
↑
delay time
from RD
↑
RD low-level width
t
DRST
0.5T–17
ns
t
WRL
V
DD
= +5.0 V
±
10%
(1.5+n)T–30
ns
(1.5+n)T–40
ns
Address hold time
(from WR
↑
)
WR
↓
delay time from
address
t
HWA
0.5T–14
ns
t
DAW
V
DD
= +5.0 V
±
10%
(1+a)T–5
ns
(1+a)T–15
ns
Data output delay time
from ASTB
↓
t
DSTOD
V
DD
= +5.0 V
±
10%
0.5T+19
ns
0.5T+35
ns
Data output delay time
from WR
↓
WR
↓
output delay time
from ASTB
↓
t
DWOD
0.5T–11
ns
t
DSTW
0.5T–9
ns
Remark
T : T
CYK
(system clock cycle time)
a : 1 (during address wait), otherwise, 0
n : Number of wait states (n
≥
0)
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