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參數(shù)資料
| 型號(hào)： | UPD78365AGF-3B9 |
| 廠商： | NEC Corp. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No |
| 中文描述： | 16/8-BIT單晶片微控制器 |
| 文件頁(yè)數(shù)： | 32/96頁(yè) |
| 文件大?。?/td> | 502K |
| 代理商： | UPD78365AGF-3B9 |
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μ
PD78363A, 78365A, 78366A, 78368A
32
3.5
CLOCK GENERATOR CIRCUIT
The clock generator circuit generates and controls the internal system clock (CLK) that is supplied to the CPU.
Figure 3-2. Block Diagram of Clock Generator Circuit
X1
X2
f
XX
or
f
X
f
CLK
1/2
System
cloock
oscillator
circuit
Internal system
clock (CLK)
STOP mode
Frequency
divider
1/2
PLL
control
circuit
Frequency
divider
Remarks 1.
f
XX
: crystal oscillation frequency
f
X
: external clock frequency
f
CLK
: internal system clock frequency
2.
3.
By connecting an 8-MHz crystal resonator across the X1 and X2 pins, an internal system clock of up to 16
MHz (f
CLK
) can be generated.
The system clock oscillation circuit oscillates by using the crystal resonator connected across the X1 and
X2 pins. It stops oscillation in standby mode.
An external clock can also be input. To do so, input the clock signal to the X1 pin and leave the X2 pin open.
Caution
Do not set STOP mode when the external clock is used.
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