參數(shù)資料
型號(hào)： UPD78322GJ-XXX-5BJ
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP74
封裝： 20 X 20 MM, PLASTIC, QFP-74
文件頁(yè)數(shù)： 62/90頁(yè)
文件大?。?/td> 649K
代理商： UPD78322GJ-XXX-5BJ
63
PD78320, 78322
Mnemonic
Bytes
Operation
Flags
S
Z
AC P/V CY
Operand
(DE + ) – (HL + ), C
← C–1
End if C=0 or CY=0
(DE – ) – (HL – ), C
← C–1
End if C=0 or CY=0
(DE + ) – A, C
← C–1
End if C=0 or CY=1
(DE – ) – A, C
← C–1
End if C=0 or CY=1
(DE + ) – (HL + ), C
← C–1
End if C=0 or CY=1
(DE – ) – (HL – ), C
← C–1
End if C=0 or CY=1
STBC
← byteNote
WDM
← byteNote
RSS
← RSS
RBS2–0
← n, RSS ← 0
RBS2–0
← n, RSS ← 1
No Operation
IE
← 1 (Enable Interrupt)
IE
← 0 (Disable Interrupt)
[DE – ], A
[DE + ], [HL + ]
[DE – ], [HL – ]
STBC, #byte
WDM, #byte
RBn
RBn, ALT
[DE + ], [HL + ]
[DE – ], [HL – ]
[DE + ], A
2
4
1
2
1
CMPBKC
CMPMNC
CMPBKNC
MOV
SWRS
SEL
NOP
EI
DI
×××
V
×
××
×
V
×
××
×
V
×
××
×
V
×
××
×
V
×
××
×
V
×
String
instruction
CPU
control
instruction
Instruction
Group
Note
If the operation code of STBC register and WDM register manipulation instructions is abnormal, an operation
code trap interrupt is generated.
Operation in the event of trap:
(SP–1)
← PSWH, (SP–2) ← PSWL,
(SP–3)
← (PC–4)H, (SP–4) ← (PC–4)L,
PCL
← (003CH), PCH ← (003DH),
SP
← SP–4, IE ← 0
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