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| 型號(hào)： | UPD78322GJ-XXX-5BJ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP74 |
| 封裝： | 20 X 20 MM, PLASTIC, QFP-74 |
| 文件頁數(shù)： | 38/90頁 |
| 文件大小： | 649K |
| 代理商： | UPD78322GJ-XXX-5BJ |
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41
PD78320, 78322
3.10 WATCHDOG TIMER
The watchdog timer is used to prevent program overrun and deadlock. Normal operation of the program or system can
be confirmed by checking that no watchdog timer interrupt has been generated. Thus, an instruction to clear the watchdog
timer (timer start) is set into each program module.
If the watchdog timer clear instruction is not cleared within the time period set into the watchdog timer and the watchdog
timer overflows, a watchdog timer interrupt is generated, and a low level is generated to WDTO pin, thereby notifying of
an error in the program.
The watchdog timer can also be used to maintain the oscillation stabilization time of the oscillator after the stop mode
has been released.
Figure 3-8 shows the watchdog timer configuration.
Figure 3-8. Watchdog Timer Configuration
fCLK/28
fCLK/210
fCLK/212
Watchdog Timer (8 Bits)
Clear
Timer (5 Bits)
Oscillation Stabilization
Time Controller
INTWDT
WDTO
WDT CLR
WDT STOP
Overflow
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