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參數(shù)資料
| 型號： | UPD78320 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/8-BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | 16/8-BIT單片機(jī) |
| 文件頁數(shù)： | 49/88頁 |
| 文件大?。?/td> | 479K |
| 代理商： | UPD78320 |
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49
μ
PD78320, 78322
7.
OPERATION AFTER RESET
If the RESET input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status
(reset status). If RESET input becomes high level, the reset state is released and program execution is started. Initialize
the contents of various registers in the program as required.
Change the number of cycles for the programmable wait control register and the fetch cycle control register as required
in particular.
The RESET input pin is equipped with an analog delay noise eliminator to prevent malfunctioning due to noise.
Cautions 1. While RESET is active (low level), all pins remain high impedance (except WDTO, AV
REF
, AV
DD
, AV
SS
,
V
DD
, V
SS
, X1 and X2).
2. If RAM has been expanded externally, mount a pull-up resistor to the P90/RD and P91/WR pins. It is
possible that the P90/RD and P91/WR pins become high impedance resulting in an external RAM
contents corruption. In addition, signals may collide on the address/data bus, resulting in the
destruction of the input/output circuit.
Figure 7-1. Reset Signal Acknowledge
For reset operation upon power-up, secure the oscillation stabilization time of about 40 msec from power-up to reset
acknowledge as shown in Figure 7-2.
Figure 7-2. Reset Upon Power-Up
RESET Input
Analog
Delay
Eliminated
as Noise
Analog
Delay
Reset
Acknowl-
edged
Analog
Delay
Reset
Release
Oscillation
Stabilization
Time
Analog
Delay
Reset
Release
V
DD
RESET
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