
4
μ
PD78044H, 78045H, 78046H
FUNCTIONAL OUTLINE
Internal
memory
Item
Product name
Instruction
cycle
ROM
Internal high-speed RAM
FIP display RAM
General registers
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
Variable instruction execution time
For main system clock
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s (at 5.0 MHz)
122
μ
s (at 32.768 kHz)
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit (set, reset, test, Boolean algebra)
For subsystem clock
Instruction set
I/O ports (including those
Total
: 68 lines
multiplexed with FIP pins)
CMOS input
:
2 lines
CMOS I/O
: 19 lines
N-ch open-drain
: 13 lines
P-ch open-drain I/O
: 16 lines
P-ch open-drain output
: 18 lines
FIP controller/driver
Total
: 34 lines
Segments
: 9 to 24 lines
Digits
: 2 to 16 lines
A/D converter
8-bit resolution
×
8 channels
Power supply voltage: AV
DD
= 4.0 to 5.5 V
Serial interface
3-wire serial I/O mode
: 1 channel
Timer
16-bit timer/event counter : 1 channel
8-bit timer/event counter : 2 channels
Watch timer
: 1 channel
Watchdog timer
: 1 channel
Timer output
3 lines (one for 14-bit PWM output)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(main system clock: when operating at 5.0 MHz)
32.768 kHz (subsystem clock: when operating at 32.768 kHz)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz (main system clock: when operating at 5.0 MHz)
Maskable interrupt
Internal 8 lines, external 4 lines
Non-maskable interrupt
Internal 1 line
Software interrupt
1 line
Text input
Internal 1 line
Power supply voltage
V
DD
= 2.7 to 5.5 V
Package
80-pin plastic QFP (14
×
20 mm)
Vectored
interrupt
μ
PD78044H
μ
PD78045H
μ
PD78046H
32K bytes
1024 bytes
48 bytes
40K bytes
48K bytes