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Chapter 16
CAN Controller
User’s Manual U16504EE1V1UD00
16.15 Function Control
16.15.1 Transmit Control
(1)
Transmit control register
This register controls the transmission of the DCAN-module. The transmit control register (TCR)
provides complete control over the two transmit buffers and their status. It is possible to request
and abort transmission of both buffers independently.
TCR can be set with a an 8-bit memory manipulation instruction.
RESET input sets TCR to 00H.
Figure 16-45:
Transmit Control Register (1/2)
Caution:
Don't use bit operations on this register. Also logical operations (read-modify-write)
via software may lead to unexpected transmissions. Initiating a transmit request for
buffer 1 while TXRQ0 is already set, is simply achieved by writing 02H or 82H. The
status of the bits for buffer 0 is not affected by this write operation.
The user defines which buffer has to be send first in the case of both request bits are set. If only one
buffer is requested by the TXRQn bits (n = 0, 1) bits, TXP bit has no influence.
TXCn (n = 0, 1) shows the status of the first transmission. It is updated when TXRQn (n = 0, 1) is
cleared.
The TXAn bits (n = 0, 1) allow to free a transmit buffer with a pending transmit request. Setting the
TXAn bit (n = 0, 1) by the CPU requests the DCAN to empty its buffer by clearing the respective TXRQn
bit (n = 0, 1).
Symbol
TCR
7
6
0
R
5
4
3
2
1
0
Address
FFB1H
After Reset
00H
TXP
R/W
TXC1
R
TXC0
R
TXA1
R/W
TXA0
R/W
TXRQ1
R/W
TXRQ0
R/W
TXP
Transmission Priority
0
Buffer 0 has priority over buffer 1
1
Buffer 1 has priority over buffer 0
TXAn
Transmission Abort Flag
0
Write: normal operation
Read: no abort pending
1
Write: aborts current transmission request for this buffer n
Read: abort is pending
TXCn
Transmission Complete Flag
0
Transmit was aborted / no data sent
1
Transmit was complete / abort had no effect