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Chapter 7
8-Bit Timer/Event Counters 50 and 51
User’s Manual U16504EE1V1UD00
7.4.3 Square-wave output
A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare
registers (CR50 and CR51).
The TO50/P34/527/TI50 or TO51/P91/522/TI51 pin output status is reversed at intervals of the count
value preset to CR50 or CR51 by setting bit 1 (TMC501) and bit 0 (TOE50) of the 8-bit timer output
control register 5 (TMC50), or bit 1 (TMC511) and bit 0 (TOE51) of the 8-bit timer mode control
register 6 (TMC51) to 1.
This enables a square wave of a selected frequency to be output.
Figure 7-14:
8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation
Setting Method
(1)
Set the registers
Set the port latch and port mode register to 0.
TCL5n
:
Selects the count clock
CR5n
:
Compare value
TMC5n
:
Selects the clear and start mode when TM5n and CR5n match.
Inversion of timer output flip-flop enabled
Timer output enabled
→
TOE5n = 1
(2)
(3)
When TCE5n = 1 is set, the counter starts operating.
When the values of TM5n and CR5n match, the timer output flip-flop inverts. Also, INTTM5n is
generated and TM5n is cleared to 00H.
Then, the timer output flip-flop is inverted for the same interval to output a square wave from
TO5n.
(4)
Caution:
When TIO50/P34/S27 or TIO51/P91/S22 pin is used as the timer output, set port mode
register (PM26 or PM27), and output latch to 0.
Remarks: 1.
n = 50, 51
2.
TMC5n4 is only available at TM51.
LVS5n
LVR5n
Setting State of Timer Output flip-flop
1
0
High level output
0
1
Low level output
1
TCEn
0
TMCn6
0
0
0/1
LVSn LVRn TMCn1 TOEn
TMCn
0/1
1
1
TOn output enable
Inversion of output on match of TMn and CRn
Specifies TO1 output F/F1 initial value
Clear and start mode on match of TMn and CRn
TMn operation enable
TM5n cascadation enable
TMCn4