參數(shù)資料
型號: UPD753208
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 4位單晶片微控制器
文件頁數(shù): 63/80頁
文件大?。?/td> 577K
代理商: UPD753208
63
μ
PD753204, 753206, 753208
SBI Mode (SCK...Internal clock output (master)): (T
A
= –40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY3
V
DD
= 2.7 to 5.5 V
1300
ns
3800
ns
SCK high/low-level
t
KL3
, t
KH3
V
DD
= 2.7 to 5.5 V
t
KCY3
/2 – 50
ns
width
t
KCY3
/2 – 150
ns
SB0, 1 setup time
(to SCK
)
t
SIK3
V
DD
= 2.7 to 5.5 V
150
ns
500
ns
SB0, 1 hold time
(from SCK
)
t
KSI3
V
DD
= 2.7 to 5.5 V
t
KCY3
/2
ns
SB0, 1 output delay
time from SCK
t
KSO3
R
L
= 1 k
,
C
L
= 100 pF
Note
V
DD
= 2.7 to 5.5 V
0
250
ns
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY3
ns
SCK
from SB0, 1
t
SBK
t
KCY3
ns
SB0, 1 low-level width
t
SBL
t
KCY3
ns
SB0, 1 high-level width
t
SBH
t
KCY3
ns
Note
R
L
and C
L
are the load resistance and load capacitance of the SB0 and SB1 output lines.
SBI Mode (SCK...External clock input (slave)): (T
A
= –40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY4
V
DD
= 2.7 to 5.5 V
800
ns
3200
ns
SCK high/low-level
t
KL4
, t
KH4
V
DD
= 2.7 to 5.5 V
400
ns
width
1600
ns
SB0, 1 setup time
(to SCK
)
t
SIK4
V
DD
= 2.7 to 5.5 V
100
ns
150
ns
SB0, 1 hold time
(from SCK
)
t
KSI4
V
DD
= 2.7 to 5.5 V
t
KCY4
/2
ns
SB0, 1 output delay
time from SCK
t
KSO4
R
L
= 1 k
,
C
L
= 100 pF
Note
V
DD
= 2.7 to 5.5 V
0
300
ns
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY4
ns
SCK
from SB0, 1
t
SBK
t
KCY4
ns
SB0, 1 low-level width
t
SBL
t
KCY4
ns
SB0, 1 high-level width
t
SBH
t
KCY4
ns
Note
R
L
and C
L
are the load resistance and load capacitance of the SB0 and SB1 output lines.
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