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參數(shù)資料
| 型號： | UPD75306BGK |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 50/76頁 |
| 文件大小： | 572K |
| 代理商： | UPD75306BGK |
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50
μ
PD75304B,75306B,75308B
DC CHARACTERISTICS (Ta = –40 to +85
°
C, V
DD
= 2.7 to 6.0 V) (2/2)
Ports 4 and 5
V
OUT
= V
DD
–2.0 V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Ports 0, 1, 2, 3, 6
and 7 (Except P00)
V
IN
= 0 V
V
DD
= 5.0 V
±
10%
15
40
80
k
R
L1
V
DD
= 3.0 V
±
10%
30
300
k
V
DD
= 5.0 V
±
10%
15
40
70
k
R
L2
V
DD
= 3.0 V
±
10%
10
60
k
LCD drive voltage
V
LCD
2.0
V
DD
V
LCD split resistor
R
LCD
60
100
150
k
LCD output voltage
deviation
*1
(common)
V
ODC
I
O
=
±
5
μ
A
0
±
0.2
V
LCD output voltage
deviation
(segment)
V
ODS
I
O
=
±
1
μ
A
0
±
0.2
V
V
DD
= 5 V
±
10%
*4
3.0
9
mA
I
DDI
4.19 MHz
*3
crystal oscillation
C1 = C2 = 22 pF
V
DD
= 3 V
±
10%
*5
0.4
1.2
mA
HALT
mode
V
DD
= 5 V
±
10%
600
1800
μ
A
I
DD2
V
DD
= 3 V
±
10%
180
540
μ
A
I
DD3
V
DD
= 3 V
±
10%
40
120
μ
A
32 kHz
*6
crystal oscillation
HALT
mode
V
DD
= 3 V
±
10%
V
DD
= 5 V
±
10%
1
25
μ
A
I
DD5
0.5
15
μ
A
Ta = 25
°
C
0.5
5
μ
A
*
1.
The voltage deviation is the difference between the output voltage and the segment or common output
desired value (V
LCDn
; n= 0, 1, 2).
2.
Current which flows in the on-chip pull-up resistor or LCD split resistor is not included.
3.
Including oscillation of the subsystem clock.
4.
When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-
speed mode.
5.
When PCC is set to 0000 and the device is operated in the low-speed mode.
6.
When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem
clock, with main system clock oscillation stopped.
I
DD4
12
36
μ
A
V
DD
=
3 V
±
10%
XT1 = 0 V
STOP mode
V
LCD0
= V
LCD
V
LCD1
= V
LCD
×
2/3
V
LCD2
= V
LCD
×
1/3
2.7 V
≤
V
LCD
≤
V
DD
On-chip pull-up
resistor
Supply current
*2
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