
42
μ
PD75304B,75306B,75308B
Operation
Skip Condition
Operand
Mne-
monic
Address-
ing Area
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
*6
*7
*8
*6
(fmem.bit) = 1
(pmem.@L) = 1
(@H + mem.bit) = 1
2
2
2
2
2
2
2
2
2
2
2
2
—
3
1
2
3
fmem.bit
pmem.@L
@H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
addr
!addr
$addr
!caddr
!addr
Note
Instruction Group
Note
SKTCLR
AND1
OR1
XOR1
BR
BRCB
CALL
BytesCycles
2 + S
2 + S
2 + S
2
2
2
2
2
2
2
2
2
—
3
2
2
3
S
B
M
Skip if (fmem.bit) = 1 and clear
Skip if (pmem
7–2
+ L
3–2
.bit (L
1–0
)) = 1 and clear
Skip if (H + mem
3–0
.bit) = 1 and clear
CY
←
CY
∧
(fmem.bit)
CY
←
CY
∧
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
∧
(H + mem
3-0
.bit)
CY
←
CY
∨
(fmem.bit)
CY
←
CY
∨
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
∨
(H + mem
3-0
.bit)
CY
←
CY
∨
(fmem.bit)
CY
←
CY
∨
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
∨
(H + mem
3-0
.bit)
G
μ
PD75304B
PC
11–0
←
addr
(The assembler selects the optimum
instruction from among the BRCB !caddr,
and BR $addr instructions.)
G
μ
PD75306B, 75308B
PC
12–0
←
addr
(The assembler selects the optimum
instruction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
G
μ
PD75306B, 75308B
PC
12–0
←
addr
G
μ
PD75304B
PC
11–0
←
addr
G
μ
PD75306B, 75308B
PC
12–0
←
addr
G
μ
PD75304B
PC
11–0
←
caddr
11–0
G
μ
PD75306B, 75308B
PC
12–0
←
PC
12
+ caddr
11–0
G
μ
PD75304B
(SP – 4) (SP – 1) (SP – 2)
←
PC
11–0
(SP – 3)
←
MBE, 0, 0, 0
PC
11–0
←
addr, SP
←
SP – 4
G
μ
PD75306B, 75308B
(SP – 4) (SP – 1) (SP – 2)
←
PC
11–0
(SP – 3)
←
MBE, 0, 0, PC
12
PC
12–0
←
addr, SP
←
SP – 4