
22
μ
PD75304B,75306B,75308B
5.2
CLOCK GENERATOR
The operation of the clock generator is determined by the processor clock control register (PCC) and system
clock control register (SCC).
There are two kinds of clock, the main system clock and subsystem clock, and the instruction execution time
can be changed.
0.95
μ
s/1.91
μ
s/15.3
μ
s (4.19 MHz main system clock operation)
122
μ
s (32.768 kHz subsystem clock operation)
Fig. 5-1 Clock Generator Block Diagram
Remarks
1.
2.
3.
4.
5.
6.
f
X
= Main system clock frequency
f
XT
= Subsystem clock frequency
PCC: Processor clock control register
SCC: System clock control register
*
indicates instruction execution.
One
Φ
clock cycle (t
CY
) is one machine cycle. See "AC CHARACTERISTICS" in
11. "ELECTRICAL
SPECIFICATIONS"
for details of t
CY
.
#
Subsystem
Clock Oscil-
lation Circuit
XT1
XT2
X1
X2
V
DD
V
DD
f
XT
f
X
LCD Controller/
Driver
Watch Timer
Basic Interval Timer (BT)
Timer/Event Counter
Serial Interface
Watch Timer
LCD Controller/Driver
INT0 Noise Elimination Circuit
Clock Output Circuit
1/8 to 1/4096
Frequency Divider
1/2
S
S
Frequency
Divider
1/4
CPU
INT0 Noise
Elimination Circuit
Clock Output Circuit
HALT F/F
S
Wait Release Signal from BT
RESET Signal
Standby Release Signal from
Interrupt Control Circuit
STOP F/F
Q
S
R
PCC2,
PCC3
Clear
Oscil-
lation
Stop
WM. 3
SCC
PCC
4
I
Main System
Clock Oscil-
lation Circuit
R
Q
PCC0
PCC1
PCC2
PCC3
SCC3
SCC0
HALT
*
STOP
*
Φ
1/16