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參數資料
| 型號： | UPD753017AGC |
| 廠商： | NEC Corp. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數： | 24/88頁 |
| 文件大小： | 438K |
| 代理商： | UPD753017AGC |
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24
μ
PD753012A, 753016A, 753017A
Data Sheet U11662EJ2V0DS00
6.2 Clock Generator
Operation of the clock generator is determined by the processor clock control register (PCC) and system clock
control register (SCC).
The two clocks, the main system clock and subsystem clock, are available.
The instruction excution time can be altered.
0.95
μ
s, 1.91
μ
s, 3.81
μ
s, 15.3
μ
s (main system clock : at 4.19 MHz operation)
0.67
μ
s, 1.33
μ
s, 2.67
μ
s, 10.7
μ
s (main system clock : at 6.0 MHz operation)
122
μ
s (subsystem clock : at 32.768 kHz operation)
Figure 6-1. Clock Generator Block Diagram
Note
Instruction execution
Remarks 1.
f
X
= Main system clock frequency
f
XT
= Subsystem clock frequency
Φ
= CPU clock
PCC: Processor Clock Control Register
SCC: System Clock Control Register
One clock cycle (t
CY
) of
Φ
equal to one machine cycle of the instruction.
2.
3.
4.
5.
6.
V
DD
V
DD
XT1
X1
XT2
X2
f
XT
f
X
Subsystem
clock oscillator
Main system
clock oscillator
4
HALT
Note
STOP
Note
WM.3
SCC
SCC3
SCC0
PCC0
PCC1
PCC2
PCC3
PCC2,
PCC3
Clear
STOP F/F
Q
S
R
Oscillation
stop
HALT F/F
S
R
Wait release signal from BT
RESET signal
Standby release signal from
interrupt control circuit
· CPU
· INT0 noise elimination circuit
· Clock output circuit
Φ
1/4
Divider
1/1 to 1/4096
Divider
1/21/41/16
· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· LCD controller/driver
· INT0 noise elimination circuit
· Clock output circuit
LCD controller/driver
Watch timer
PCC
Q
Selector
Selector
I
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