
155
μ
PD75237
*1
MB = MBE MBS
(MBS = 0, 1, 2, 3, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (00H to 7FH)
MB = 15 (80H to FFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 2, 3, 15)
*4
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
addr = 0000H to 3FFFH
*7
addr = (Current PC) – 15 to (Current PC) – 1,
(Current PC) + 2 to (Current PC) + 16
*8
caddr = 0000H to 0FFFH
1000H to 1FFFH
2000H to 2FFFH
3000H to 3FFFH
4000H to 4FFFH
5000H to 5F7FH
(PC
14, 13, 12
= 00B) or
(PC
14, 13, 12
= 01B) or
(PC
14, 13, 12
= 10B) or
(PC
14, 13, 12
= 11B) or
(PC
14, 13, 12
= 100B) or
(PC
14, 13, 12
= 101B)
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
*11
addr1 = 0000H to 5F7FH
(3)
Description of symbols in the addressing area column
Data Memory
Addressing
Program Memory
Addressing
Remarks 1.
MB indicates accessible memory bank.
In *2, MB = 0 irrespective of MBE and MBS.
In *4 and *5, MB = 15 irrespective of MBE and MBS.
*6 to *10 indicate addressable areas.
2.
3.
4.
(4)
Description of the machine cycle column
S indicates the number of machine cycles required for skip operation by an instruction having skip function.
The S value varies as follows:
When not skipped .............................................................................. S = 0
When 1-byte or 2-byte instructions are skipped............................ S = 1
When 3-byte instructions are skipped............................................. S = 2
Note
GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of CPU clock
Φ
and five time periods are available according to
PCC and SCC setting. (Refer to
4.2 (3) Processor clock control register (PCC)
.)