參數(shù)資料
型號(hào): UPD75208
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機(jī)
文件頁(yè)數(shù): 48/62頁(yè)
文件大?。?/td> 497K
代理商: UPD75208
48
μ
PD75208
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40
to +85
°
C)
2.0
6.0
V
V
DDDR
= 2.0V
0.1
10
μ
A
0
μ
s
Release by RESET
2
17
/f
X
ms
Release by interrupt request
*3
ms
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention power
supply voltage
Data retention power
supply current
*1
t
SREL
t
WAIT
V
DDDR
I
DDDR
Release signal set time
Oscillation stabilization
wait time
*2
*
1.
Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.
2.
Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation
start.
3.
According to the setting of the basic interval timer mode register (BTM) (see below).
BTM3
BTM2
BTM1
BTM0
Wait Time (Values at f
XX
= 4.19 MHz in parentheses)
0
0
0
2
20
/f
X
(approx. 250 ms)
0
1
1
2
17
/f
X
(approx. 31.3 ms)
1
0
1
2
15
/f
X
(approx. 7.82 ms)
1
1
1
2
13
/f
X
(approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
STOP Instruction Execution
V
DD
V
DDDR
Operating Mode
HALT Mode
STOP Mode
Data Retention Mode
t
WAIT
RESET
t
SREL
Internal Reset Operation
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