參數(shù)資料
型號: UPD75208
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機
文件頁數(shù): 25/62頁
文件大?。?/td> 497K
代理商: UPD75208
25
μ
PD75208
7.
STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the
μ
PD75208 to decrease power consump-
tion in the program standby mode.
Table 7-1 Operation Status in Standby Mode
8.
RESET FUNCTIONS
The reset signal (RES) generator has a configuration shown in Fig. 8-1.
Fig. 8-1 Reset Signal Generator
The power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power
voltage. This pulse is used in three ways according to SWA, SWB mask option specification shown in Fig. 8-1. (See
10. MASK OPTION SELECTION
.)
HALT Mode
HALT instruction
Setting enabled with either main system
clock or subsystem clock.
Stops only with CPU clock
Φ
(Oscillation
continued).
Operation (IRQBT set at reference time
intervals).
Operation enabled when serial clock other
than
Φ
is specified.
Operation enabled.
Operation enabled.
Operation enabled.
Set instruction
System clock when set
Clock oscillator
Basic interval timer
Serial interface
Timer/event counter
Timer/pulse generator
Watch timer
FIP controller/driver
CPU
STOP Mode
STOP instruction
Setting enabled only with main system
clock.
Oscillator stops only with main system
clock.
Operation stopped.
Operation enabled only when external
SCK input is selected for serial clock.
Operation enabled only when TI0 pin
input is specified for count clock.
Operation stopped.
Operation enabled only f
XT
is selected for
count clock.
O
Operation disabled (display off mode set before disabling).
Operation stopped.
Release signal
Interrupt request signal (except INT0, INT1, INT2) or RESET input enabled by
interrupt enable flag.
RESET
Power-On
Reset
Generator
Mask
Option
Internal Reset Signal
(RES)
Power-On Flag
(PONF)
I
Bit
Manipulation
Instruction
Execution
SWA
SWB
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