
2
μ
PD75116H,75117H
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
μ
PD75116HGC-
×××
-AB8
μ
PD75116HGK
-
×××
-8A8
μ
PD75117HGC-
×××
-AB8
μ
PD75117HGK
-
×××
-8A8
64-pin plastic QFP ( 14 mm)
64-pin plastic QFP ( 12 mm)
64-pin plastic QFP ( 14 mm)
64-pin plastic QFP ( 12 mm)
Standard
Standard
Standard
Standard
Remarks
×××
: ROM code number
OVERVIEW OF FUNCTIONS
Contents
43
0.95
μ
s, 1.91
μ
s, 15.3
μ
s (4.19 MHz operation)
3-stage switching capability
24448
×
8 bits (
μ
PD75117H), 16256
×
8 bits (
μ
PD75116H)
768
×
4 bits
4 bits
×
8
×
4 banks (memory mapping)
Total 58
CMOS input pins
CMOS input/output pins
: 10
: 32 (pins with LED direct drive
capability
*1
)
: 12 (pins with LED direct drive
capability
*2
)
N-ch open-drain input/output pins
(A pull-up resistor can be incorporated bit-wise.)
Comparator input pins (4-bit precision) : 4
8-bit timer/event counter
×
2
8-bit basic interval timer (watchdog timer applicable)
8 bits
LSB-first/MSB-first switchable
2 transfer modes (transmission/reception and dedicated reception modes)
External :
Internal :
3
4
External :
2
STOP/HALT mode
Various bit manipulation instructions (set, reset, test, Boolean operation)
8-bit data transfer, comparison, operation, increment/decrement instructions
1-byte relative branch instruction
GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1
byte
Bit manipulation memory (bit sequential buffer: 16 bits) on chip
64-pin plastic QFP (
64-pin plastic QFP (
14 mm)
12 mm)
Item
Basic instructions
Instruction cycle
On-chip memory
General register
Input/output port
Timer/counter
Serial interface
Vectored interrupt
Test input
Standby
Instruction set
Others
Package
ROM
RAM
* 1.
When V
DD
= 5 V, I
OL
= 15 mA.
When V
DD
= 5 V, I
OL
= 10 mA.
2.
#
#
#