
14
μ
PD75116H,75117H
Note
Since the above interrupt vector start address is a 14-bit address, set it in a 16K space (0000H to
3FFFH).
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-
order 8 bits have been changed by the BR PCDE or BR PCXA instruction.
Fig. 4-1 Program Memory Map (1/2)
(a)
μ
PD75117H
≈
≈
≈
≈
≈
≈
≈
MBE
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
7
6
0
Address
Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits)
INTBT/INT4 Start Address (High-Order 6 Bits)
INT0/INT1 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
INT0/INT1 Start Address (Low-Order 8 Bits)
INTSIO Start Address (High-Order 6 Bits)
INTSIO Start Address (Low-Order 8 Bits)
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
INTT1 Start Address (High-Order 6 Bits)
INTT1 Start Address (Low-Order 8 Bits)
GETI Instruction Reference Table
CALLF
! faddr
Instruction
Entry
Address
BRCB
! caddr
Instruction
Branch
Address
BR !addr
Instruction
Branch Address
≈
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
MBE
RBE
1FFFH
2000H
2FFFH
3000H
3FFFH
4000H
4FFFH
5000H
5F7FH
≈
≈
≈
≈
≈
≈
≈
≈
CALL !addr
Instruction
Branch Address
Branch/Call
Address
by GETI
BR BCDE
BR BCXA
Branch Address
BRA !addr1
Instruction
Branch Address
CALLA !addr1
Instruction
Branch Address
BR $addr1 Instruction
Relative Branch
Address
(-15 to -1, +2 to +16)
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address
BRCB !caddr
Instruction
Branch Address