參數(shù)資料
型號(hào): UPD75116H
廠商: NEC Corp.
英文描述: 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述: 4位單片機(jī)
文件頁數(shù): 55/66頁
文件大?。?/td> 472K
代理商: UPD75116H
55
μ
PD75116H,75117H
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +60
°
C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention supply voltage
V
DDDR
1.8
5.5
V
Data retention supply current
*1
I
DDDR
V
DDDR
= 2.0 V
0.05
10
μ
A
Release signal set time
t
SREL
0
μ
s
Release by RESET
2
17
/f
XX
ms
t
WAIT
Release by interrupt request
*3
ms
*
1.
Excluding current flowing in the internal pull-up resistors and comparator circuit.
2.
The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable
operation when oscillation is started.
3.
Depends on the basic interval timer mode register (BTM) setting (see table below).
WAIT TIME
BTM3
BTM2
BTM1
BTM0
(Figures in parentheses are for operation at f
XX
= 4.19 MHz)
0
0
0
2
20
/f
XX
(approx. 250 ms)
0
1
1
2
17
/f
XX
(approx. 31.3 ms)
1
0
1
2
15
/f
XX
(approx. 7.82 ms)
1
1
1
2
13
/f
XX
(approx. 1.95 ms)
STOP Mode
Data Retention Mode
STOP Instruction Execution
RESET
V
DD
Internal Reset Operation
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
Data Retention Timing (STOP mode release by RESET)
Oscillation stabilization wait
time
*2
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