參數(shù)資料
型號： UPD75116H
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機
文件頁數(shù)： 40/66頁
文件大小： 472K
代理商： UPD75116H
40
μ
PD75116H,75117H
Instruction
Group
Mne-
monic
Branch
BytesMachine
Cycles
Addressing
Area
Skip
Condition
Operation
Operands
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
*11
*6
*7
*11
*11
*11
*8
*6
AND1
Memory bit
manipulation
XOR1
2
2
2
2
2
2
2
2
2
—
—
3
2
2
3
3
3
3
3
2
3
4
OR1
2
2
2
2
2
2
2
2
2
—
—
3
1
1
2
2
2
2
3
2
3
BR
BRCB
BRA
Subroutine
stack
control
CALL
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H + mem.bit
addr
*1
addr1
!addr
$addr
$addr1
PCDE
PCXA
BCDE
*2
BCXA
*2
!addr1
!caddr
!addr
*
1.
μ
PD75116H only.
2.
The 3 lower bits in the B register are valid only.
Remarks
Shading indicates a part compatible with the
μ
PD75117H.
CY
←
CY
∧
(fmem.bit)
CY
←
CY
∧
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
∧
(H + mem
3–0
.bit)
CY
←
CY
∨
(fmem.bit)
CY
←
CY
∨
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
∨
(H + mem
3–0
.bit)
CY
←
CY
∨
(fmem.bit)
CY
←
CY
∨
(pmem
7–2
+ L
3–2
.bit (L
1–0
))
CY
←
CY
∨
(H + mem
3–0
.bit)
PC
13–0
←
addr
(The assembler selects the optimum in-
struction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
PC
14–0
←
addr1
(The assembler selects the optimum in-
struction from among the BR !addr, BRA
!addr1, BRCB !caddr, and BR $addr1 in-
structions.)
PC
13-0
←
addr
PC
14-0
, PC
13-0
←
addr
PC
13-0
←
addr
PC
14-0
←
addr1
PC
13-0
←
PC
13-8
+ DE
PC
14-0
←
PC
14-8
+ DE
PC
13-0
←
PC
13-8
+ XA
PC
14-0
←
PC
14-8
+ XA
PC
14-0
←
B
2-0
+ CDE
PC
14-0
←
B
2-0
+ CXA
PC
14-0
←
!addr1
PC
13-0
←
PC
13,12
+ caddr
11-0
PC
14-0
←
PC
14,13,12
+ caddr
11-0
(SP – 4) (SP – 1) (SP – 2)
←
PC
11-0
(SP – 3)
←
MBE, RBE, PC
13
, PC
12
PC
13-0
←
addr, SP
←
SP–4
(SP – 2)
←
×
,
×
, MBE, RBE
(SP – 6) (SP – 3) (SP – 4)
←
PC
11-0
(SP – 5)
←
0, PC
14
, PC
13
, PC
12
PC
14
←
0, PC
13-0
←
addr, SP
←
SP–6
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