39
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Group
Interrupt
control
Input/
output
CPU
control
Special
Mne-
monic
EI
DI
IN
OUT
HALT
STOP
NOP
SEL
GETI
Operand
IExxx
IExxx
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
MBn
taddr
Bytes
2
2
2
2
2
2
2
2
2
2
1
2
1
Ma-
chine
cycle
2
2
2
2
2
2
2
2
2
2
1
2
3
Address-
ing area
*10
Operation
IME
←
1
IExxx
←
1
IME
←
0
IExxx
←
0
A
←
PORTn (n = 0 - 6, 11)
XA
←
PORTn
+1
,PORTn
(n = 4, 6)
PORTn
←
A
(n = 2 - 6)
PORTn
+1
, PORTn
←
XA (n = 4, 6)
Set HALT Mode (PCC.2
←
1)
Set STOP Mode (PCC.3
←
1)
No Operation
MBS
←
n (n = 0, 1, 15)
μ
PD75064
For the TBR instruction
PC
←
(taddr)
+ (taddr + 1)
----------------------------------------------
For the TCALL instruction
(SP – 4)(SP – 1)(SP – 2)
←
PC
11-0
(SP – 3)
←
MBE, 0, 0, 0
PC
11-0
←
(taddr)
3-0
+ (taddr + 1)
SP
←
SP – 4
----------------------------------------------
For other than the TBR and
TCALL instruction
(taddr) (taddr + 1) is executed.
μ
PD75066, 75068
For the TBR instruction
PC
←
(taddr)
+ (taddr + 1)
----------------------------------------------
For the TCALL instruction
(SP – 4)(SP – 1)(SP – 2)
←
PC
11-0
(SP – 3)
←
MBE, 0, 0, PC
12
PC
12-0
←
(taddr)
4-0
+ (taddr + 1)
SP
←
SP – 4
----------------------------------------------
For other than the TBR and
TCALL instruction
(taddr) (taddr + 1) is executed.
-----------------
-----------------
Depends on
the refer-
ence
instruction.
-----------------
-----------------
Depends on
the refer-
ence
instruction.
Skip
condition
Caution When executing the IN/OUT instruction, MBE must be set to 0, or MBE and MBS must be set to
1 and 15, respectively.