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參數(shù)資料
| 型號(hào)： | UPD75036CW |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 15/58頁(yè) |
| 文件大?。?/td> | 485K |
| 代理商： | UPD75036CW |
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15
μ
PD75036
4. ARCHITECTURE AND MEMORY MAP OF THE
μ
PD75036
The
μ
PD75036 has two architectural features:
Bank configuration of data memory: Static RAM (1024 words
×
4 bits)
Peripheral hardware (128
×
4 bits)
Memory mapped I/O
Fig. 4-1 and 4-2 show the memory maps for the
μ
PD75036.
Fig. 4-1 Program Memory Map
Remark
In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the low-order 8 bits of the PC changed.
MBE
0
7
6
0000H
MBE
0
0002H
MBE
0
0004H
MBE
0
0006H
MBE
0
0008H
MBE
0
000AH
0020H
007FH
0080H
1FFFH
2000H
0
Internal reset start address (high-order 6 bits)
Internal reset start address (low-order 8 bits)
INTBT/INT4 start address
(high-order 6 bits)
INTBT/INT4 start address
(low-order 8 bits)
INT0 start address
(high-order 6 bits)
INT0 start address
(low-order 8 bits)
INT1 start address
(high-order 6 bits)
INT1 start address
(low-order 8 bits)
INTCSI start address (high-order 6 bits)
INTCSI start address (low-order 8 bits)
INTT0 start address
(high-order 6 bits)
INTT0 start address
(low-order 8 bits)
INTMFT start address (high-order 6 bits)
INTMFT start address (low-order 8 bits)
GETI instruction reference table
CALL !addr
instruction
subroutine
entry address
BR !addr
instruction
branch
address
BR $addr
instruction
relative
branch
address
(-15 to -1,
+2 to +16)
CALLF
!faddr
instruc-
tion
entry
address
BRCB
!caddr
instruc-
tion
branch
address
MBE
0
000CH
1000H
0FFFH
0800H
07FFH
2FFFH
3000H
Branch
address and
subroutine
entry
address
specified in
GETI
instruction
Address
0
0
0
0
0
0
0
5
3F7FH
BRCB !caddr instruc-
tion branch address
BRCB !caddr instruc-
tion branch address
BRCB !caddr instruc-
tion branch address
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