參數資料
型號: uPD750066GTA
廠商: NEC Corp.
英文描述: CONNECTOR ACCESSORY
中文描述: 連接器附件
文件頁數: 67/82頁
文件大小: 460K
代理商: UPD750066GTA
67
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V0DS00
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
A
= –40 to +85C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Release signal set time
t
SREL
0
μ
s
Oscillation stabilization
t
WAIT
Released by RESET
Note 2
ms
wait time
Note 1
Released by interrupt request
Note 3
ms
Notes 1.
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent
unstable operation when oscillation is started.
Either 2
17
/f
X
or 2
15
/f
X
can be selected by mask option.
Set by the basic interval timer mode register (BTM). (Refer to the table below.)
2.
3.
BTM3
BTM2
BTM1
BTM0
Wait Time
f
X
= 4.19 MHz
f
X
= 6.0 MHz
0
0
0
2
20
/f
X
(approx. 250 ms)
2
20
/f
X
(approx. 175 ms)
0
1
1
2
17
/f
X
(approx. 31.3 ms)
2
17
/f
X
(approx. 21.8 ms)
1
0
1
2
15
/f
X
(approx. 7.81 ms)
2
15
/f
X
(approx. 5.46 ms)
1
1
1
2
13
/f
X
(approx. 1.95 ms)
2
13
/f
X
(approx. 1.37 ms)
Data retention timing (STOP mode release by RESET)
Data retention timing (standby release signal: STOP mode release by interrupt signal)
STOP mode
Data retention mode
Internal reset operation
Operation mode
STOP instruction execution
HALT mode
V
DD
RESET
V
DDDR
t
WAIT
t
SREL
STOP mode
Data retention mode
Operation mode
HALT mode
t
SREL
V
DDDR
t
WAIT
STOP instruction execution
V
DD
Standby release signal
(interrupt request)
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