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參數(shù)資料
| 型號(hào)： | uPD750066GTA |
| 廠商： | NEC Corp. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁(yè)數(shù)： | 38/82頁(yè) |
| 文件大?。?/td> | 460K |
| 代理商： | UPD750066GTA |
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38
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V0DS00
9. RESET FUNCTION
There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/
watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-
1 shows the configuration of the above two inputs.
Figure 9-1. Configuration of Reset Function
RESET
Internal reset signal
Reset signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
When the RESET signal is generated, each hardware is initialized as listed in Table 9-1. Figure 9-2 shows
the timing chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Operation mode or
standby mode
Wait
Note
RESET
signal
generated
Operation mode
HALT mode
Internal reset operation
Note
The following two times can be selected by the mask option.
2
17
/f
X
(21.8 ms: @6.0-MHz operation, 31.3 ms: @4.19-MHz operation)
2
15
/f
X
(5.46 ms: @6.0-MHz operation, 7.81 ms: @4.19-MHz operation)
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