參數(shù)資料
型號: UPD750006A
廠商: NEC Corp.
英文描述: 4 BIT SINGLE-CHIP MICROCONTROLLER
中文描述: 4位單片機
文件頁數(shù): 66/84頁
文件大?。?/td> 719K
代理商: UPD750006A
66
μ
PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
Parameter
Symbol
Release signal setting time
Oscillation settling time
Note 1
t
SREL
t
WAIT
Note 2
Note 3
Release by RESET
Release by interrupt request
Conditions
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE
(T
A
= -40 to +85
°
C)
Notes 1.
CPU operation stop time for preventing unstable operation at the beginning of oscillation.
2.
Select either 2
17
/f
X
or 2
15
/f
X
with the mask option.
3.
This value depends on the settings of the basic interval timer mode register (BTM) shown below.
Data hold timing (STOP mode release by RESET)
Data hold timing (standby release signal: STOP mode release by interrupt signal)
-
-
-
-
0
1
0
1
0
1
1
1
0
0
1
1
2
20
/f
X
(approx. 250 ms)
2
17
/f
X
(approx. 31.3 ms)
2
15
/f
X
(approx. 7.81 ms)
2
13
/f
X
(approx. 1.95 ms)
0
Min.
Typ.
Max.
Unit
μ
s
ms
ms
2
20
/f
X
(approx. 175 ms)
2
17
/f
X
(approx. 21.8 ms)
2
15
/f
X
(approx. 5.46 ms)
2
13
/f
X
(approx. 1.37 ms)
Wait time
At f
X
= 4.19 MHz
At f
X
= 6.0 MHz
Standby release signal
(Interrupt request)
V
DD
t
SREL
t
WAIT
HALT mode
Operation
mode
STOP instruction execution
Data hold mode
STOP mode
RESET
V
DD
t
SREL
t
WAIT
Internal reset operation
HALT mode
Operation
mode
STOP instruction execution
Data hold mode
STOP mode
BTM3
BTM2
BTM1
BTM0
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