參數(shù)資料
型號： UPD70F3025AGC-25-8EU
廠商： NEC Corp.
英文描述： V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述： V853TM 32-/16-BIT單片機
文件頁數(shù)： 22/44頁
文件大小： 295K
代理商： UPD70F3025AGC-25-8EU
μ
PD70F3003A, 70F3025A
22
Data Sheet U13189EJ3V0DS00
(5) Read timing (1/2)
Parameter
Symbol
Condition
25 MHz Model
33 MHz Model
Unit
MIN.
MAX.
MIN.
MAX.
CLKOUT
↑→
address delay time
<20>
t
DKA
3
20
3
20
ns
CLKOUT
↑→
R/W, UBEN, LBEN delay time
<78>
t
DKA2
–2
+13
–2
+13
ns
CLKOUT
↑→
address float delay time
<21>
t
FKA
3
15
3
15
ns
CLKOUT
↓→
ASTB delay time
<22>
t
DKST
3
15
3
15
ns
CLKOUT
↓→
DSTB delay time
<23>
t
DKD
3
15
3
15
ns
Data input setup time (vs. CLKOUT
↑
)
<24>
t
SIDK
5
5
ns
Data input hold time (vs. CLKOUT
↑
)
<25>
t
HKID
5
5
ns
WAIT setup time (vs. CLKOUT
↓
)
WAIT hold time (vs. CLKOUT
↓
)
<26>
t
SWTK
5
5
ns
<27>
t
HKWT
5
5
ns
Address hold time (vs. CLKOUT
↑
) <28>
t
HKA
0
0
ns
Address setup time (vs. ASTB
↓
)
<29>
t
SAST
–40
°
C
≤
T
A
≤
+70
°
C
0.5 T – 10
0.5 T – 10
ns
70
°
C
<
T
A
≤
85
°
C
0.5 T – 12
0.5 T – 12
ns
Address hold time (vs. ASTB
↓
)
<30>
t
HSTA
0.5 T – 10
0.5 T – 10
ns
DSTB
↓→
address float delay time <31>
t
FDA
0
0
ns
Data input setup time (vs. address)
<32>
t
SAID
–40
°
C
≤
T
A
≤
+70
°
C
(2 + n) T – 22
(2 + n) T – 22
ns
70
°
C
<
T
A
≤
85
°
C
(2 + n) T – 25
(2 + n) T – 25
ns
Data input setup time (vs. DSTB
↓
)
<33>
t
SDID
–40
°
C
≤
T
A
≤
+70
°
C
(1 + n) T – 20
(1 + n) T – 20
ns
70
°
C
<
T
A
≤
85
°
C
(1 + n) T – 24
(1 + n) T – 24
ns
ASTB
↓→
DSTB
↓
delay time
Data input hold time (vs. DSTB
↑
)
<34>
t
DSTD
0.5 T – 10
0.5 T – 10
ns
<35>
t
HDID
0
0
ns
DSTB
↑→
address output delay time
<36>
t
DDA
(1 + i) T
(1 + i) T
ns
DSTB
↑→
ASTB
↑
delay time
<37>
t
DDSTH
0.5 T – 10
0.5 T – 10
ns
DSTB
↑→
ASTB
↓
delay time
<38>
t
DDSTL
(1.5 + i) T – 10
(1.5 + i) T – 10
ns
DSTB width, low
<39>
t
WDL
–40
°
C
≤
T
A
≤
+70
°
C
(1 + n) T – 10
(1 + n) T – 10
ns
70
°
C
<
T
A
≤
85
°
C
(1 + n) T – 13
(1 + n) T – 13
ns
ASTB width, high
<40>
t
WSTH
T – 10
T – 10
ns
WAIT setup time (vs. address)
<41>
t
SAWT1
n
≥
1, –40
°
C
≤
T
A
≤
+70
°
C
1.5 T – 20
1.5 T – 20
ns
n
≥
1, 70
°
C
<
T
A
≤
85
°
C
1.5 T – 24
1.5 T – 24
ns
<42>
t
SAWT2
n
≥
1, –40
°
C
≤
T
A
≤
+70
°
C
(1.5 + n) T – 20
(1.5 + n) T – 20
ns
n
≥
1, 70
°
C
<
T
A
≤
85
°
C
n
≥
1
(1.5 + n) T – 24
(1.5 + n) T – 24
ns
WAIT hold time (vs. address)
<43>
t
HAWT1
(0.5 + n) T
(0.5 + n) T
ns
<44>
t
HAWT2
n
≥
1
(1.5 + n) T
(1.5 + n) T
ns
WAIT setup time (vs. ASTB
↓
)
<45>
t
SSTWT1
n
≥
1, –40
°
C
≤
T
A
≤
+70
°
C
T – 18
T – 18
ns
n
≥
1, 70
°
C
<
T
A
≤
85
°
C
T – 20
T – 20
ns
<46>
t
SSTWT2
n
≥
1
(1 + n) T – 15
(1 + n) T – 15
ns
WAIT hold time (vs. ASTB
↓
)
<47>
t
HSTWT1
n
≥
1
n
≥
1
nT
nT
ns
<48>
t
HSTWT2
(1 + n) T
(1 + n) T
ns
Remarks 1.
T = t
CYK
2.
n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
3.
i indicates the number of idle states (0 or 1) t be inserted in the read cycle.
4.
Be sure to observe at least one of data input hold times t
HKID
(<25>) and t
HDID
(<35>).
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