
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User
’
s Manual U15862EJ3V0UD
364
8.4.5 Operation as interval timer (16 bits)
The V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are provided with a 16-bit register that can be used only during
cascade connection.
The 16-bit resolution timer/event counter mode is selected by setting the TMC514 bit of 8-bit timer mode control
register 51 (TMC51) to 1.
8-bit timer/event counter 5n operates as an interval timer by repeatedly generating interrupts using the count value
preset in 16-bit timer compare register 5 (CR5) as the interval.
Setting method
<1>
Set each register.
TCL50 register:
Selects the count clock (t)
(The TCL51 register does not need to be set in cascade connection)
Compare value (N) ... Lower 8 bits (settable from 00H to FFH)
Compare value (N) ... Higher 8 bits (settable from 00H to FFH)
Selects the mode in which clear & start occurs on a match between TM5
register and CR5 register (
×
: don
’
t care)
TMC50 register = 0000xx00B
TMC51 register = 0001xx00B
Set the TCE51 bit of the TMC51 register to 1. Then set the TCE50 bit of the TMC50 register to 1 to start
the count operation.
When the values of the TM5 register and CR5 register connected in cascade match, INTTM50 is
generated (the TM5 register is cleared to 0000H).
INTTM50 is then generated repeatedly at the same interval.
CR50 register:
CR51 register:
TMC50, TMC51 register:
<2>
<3>
<4>
Interval time = (N + 1)
×
t: N = 0000H to FFFFH
Cautions 1. To write using 8-bit access during cascade connection, set the TCE51 bit to 1 at
operation start and then set the TCE50 bit to 1. When operation is stopped, set the
TCE50 bit to 0 and then set the TCE51 bit to 0.
2. During cascade connection, TI50 input, TO50 output, and INTTM50 signal output are
used while TI51 input, TO51 output, and INTTM51 signal output are not, so set bits
LVS51, LVR51, TMC511, and TOE51 to 0.
3. Do not change the value of the CR5 register during timer operation.