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參數(shù)資料
| 型號(hào)： | UPD70320 |
| 廠商： | NEC Corp. |
| 英文描述： | V25TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | V25TM 16/8-BIT單片機(jī) |
| 文件頁數(shù)： | 28/74頁 |
| 文件大?。?/td> | 439K |
| 代理商： | UPD70320 |
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2
μ
P
SHR
SHRA
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
Operation Code
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
3
3 to 5
2
2 to 4
2
2 to 4
3
3 to 5
Bytes
Flags
AC CY V
P
S
Z
CY
←
reg LSB, reg
←
reg
÷
2
reg MSB
≠
bit following reg MSB: V
←
1
reg MSB = bit following reg MSB: V
←
0
CY
←
(mem) LSB, (mem)
←
(mem)
÷
2
(mem) MSB
≠
bit following (mem) MSB: V
←
1
(mem) MSB = bit following (mem) MSB: V
←
0
The following operations are repeated while temp
←
CL
and temp
≠
0.
CY
←
reg LSB, reg
←
reg
÷
2
temp
←
temp – 1
The following operations are repeated while temp
←
CL
and temp
≠
0.
CY
←
(mem) LSB, (mem)
←
(mem)
÷
2
temp
←
temp – 1
The following operations are repeated while temp
←
imm8
and temp
≠
0.
CY
←
reg LSB, reg
←
reg
÷
2
temp
←
temp – 1
The following operations are repeated while temp
←
imm8
and temp
≠
0.
CY
←
(mem) LSB, (mem)
←
(mem)
÷
2
temp
←
temp – 1
CY
←
reg LSB, reg
←
reg
÷
2, V
←
0
The operand MSB remains the same status.
CY
←
(mem) LSB, (mem)
←
(mem)
÷
2, V
←
0
The operand MSB remains the same status.
The following operations are repeated while temp
←
CL
and temp
≠
0. CY
←
reg LSB, reg
←
reg
÷
2
temp
←
temp – 1
The operand MSB remains the same status.
The following operations are repeated while temp
←
CL
and temp
≠
0. CY
←
(mem) LSB, (mem)
←
(mem)
÷
2
temp
←
temp – 1
The operand MSB remains the same status.
The following operations are repeated while temp
←
imm8
and temp
≠
0. CY
←
reg LSB, reg
←
reg
÷
2
temp
←
temp – 1
The operand MSB remains the same status.
The following operations are repeated while temp
←
imm8
and temp
≠
0. CY
←
(mem) LSB, (mem)
←
(mem)
÷
2
temp
←
temp – 1
The operand MSB remains the same status.
Operation
Shift
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 1 1 reg
mod 1 1 1 mem
1 1 1 1 1 reg
mod 1 1 1 mem
1 1 1 1 1 reg
mod 1 1 1 mem
U
U
U
U
U
U
U
U
U
U
U
U
×
×
×
×
×
×
×
×
×
×
×
×
×
×
U
U
U
U
0
0
U
U
U
U
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
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