參數(shù)資料
型號(hào): UPD703031AYGC
廠商: NEC Corp.
英文描述: V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850/SB1TM 32-/16-BIT單晶片微控制器
文件頁(yè)數(shù): 42/56頁(yè)
文件大?。?/td> 357K
代理商: UPD703031AYGC
Data Sheet U14734EJ1V0DS00
42
μ
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(9) 3-wire variable length serial interface (CSI4) timing
(a) Master mode (T
A
= –40 to +85
°
C, V
DD
= 4.0 to 5.5 V, EV
DD
= 3.0 to 5.5 V, V
SS
= EV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
4.0 V
EV
DD
5.5 V
200
ns
SCK4 cycle
<68>
t
KCY1
3.0 V
EV
DD
< 4.0 V
400
ns
4.0 V
EV
DD
5.5 V
60
ns
SCK4 high-level width
<69>
t
KH1
3.0 V
EV
DD
< 4.0 V
140
ns
4.0 V
EV
DD
5.5 V
60
ns
SCK4 low-level width
<70>
t
KL1
3.0 V
EV
DD
< 4.0 V
140
ns
4.0 V
EV
DD
5.5 V
25
ns
SI4 setup time (to SCK4
)
<71>
t
SIK1
3.0 V
EV
DD
< 4.0 V
50
ns
SI4 hold time (from SCK4
)
<72>
t
KSI1
20
ns
Delay time from SCK4
to SO4
output
<73>
t
KSO1
55
ns
(b) Slave mode (T
A
= –40 to +85
°
C, V
DD
= 4.0 to 5.5 V, EV
DD
= 3.0 to 5.5 V, V
SS
= EV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
4.0 V
EV
DD
5.5 V
200
ns
SCK4 cycle
<68>
t
KCY2
3.0 V
EV
DD
< 4.0 V
400
ns
4.0 V
EV
DD
5.5 V
60
ns
SCK4 high-level width
<69>
t
KH2
3.0 V
EV
DD
< 4.0 V
140
ns
4.0 V
EV
DD
5.5 V
60
ns
SCK4 low-level width
<70>
t
KL2
3.0 V
EV
DD
< 4.0 V
140
ns
4.0 V
EV
DD
5.5 V
25
ns
SI4 setup time (to SCK4
)
<71>
t
SIK2
3.0 V
EV
DD
< 4.0 V
50
ns
SI4 hold time (from SCK4
)
<72>
t
KSI2
20
ns
4.0 V
EV
DD
5.5 V
55
ns
Delay time from SCK4
to SO4
output
<73>
t
KSO2
3.0 V
EV
DD
< 4.0 V
100
ns
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