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| 型號(hào)： | UPD65971 |
| 英文描述： | CMOS-9HD Family Ver.6.0 Design Manual | Design Manual[07/2001] |
| 中文描述： | CMOS的9HD家庭Ver.6.0設(shè)計(jì)手冊(cè)|設(shè)計(jì)手冊(cè)[07/2001] |
| 文件頁(yè)數(shù)： | 18/64頁(yè) |
| 文件大?。?/td> | 399K |
| 代理商： | UPD65971 |
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18
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
3.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below.
When reset, the register becomes 0010 0110B.
Table 3-6. Control Register 1 (P4)
Bit
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Name
—
—
K
I
S
0
/S
1
S
2
S
1
/LED
K
I/O
S
0
Pull-down Pull-down
STOP release
mode
mode
mode
Set
0
Fixed
Fixed
OFF
OFF
Disable
S
1
IN
OFF
value
1
to “0”
to “0”
ON
ON
Enable
LED
OUT
IN
When reset
0
0
1
0
0
1
1
0
b
0
b
1
: Specifies the input mode of the S
0
port. “0” = OFF mode (high impedance); “1” = IN (INPUT mode).
: Specifies the I/O mode of the K
I/O
port.
“0” = IN (INPUT mode); “1” = OUT (OUTPUT mode).
: Specifies the I/O mode of the S
1
/LED port. “0” = S
1
(INPUT mode); “1” = LED (output mode).
: Specified the use of the STOP mode release by S
2
port (with/without pull-down resistor). “0” = disable (pull-
down unavailable); “1” = enable (pull-down available).
: Specifies the availability of the pull-down resistor in S
0
/S
1
port INPUT mode. “0” = OFF (unavailable);
“1” = ON (available)
: Specifies the availability of the pull-down resistor in K
I
port. “0” = OFF (unavailable);
“1” = ON (available).
b
2
b
3
b
4
b
5
Remark
In OUTPUT mode or in OFF mode, all the pull-down resistors are automatically disconnected.
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